XC5VLX50T-1FFG1136C Xilinx Inc, XC5VLX50T-1FFG1136C Datasheet - Page 202

• Manufacturer Part Number: XC5VLX50T-1FFG1136C
• Description: IC FPGA VIRTEX-5 50K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG1136C

• Total Ram Bits: 2211840
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• No. Of Logic Blocks: 7200
• No. Of Gates: 50000
• Family Type: Virtex-5 LXT
• No. Of Speed Grades: 1
• No. Of I/o's: 480
• Clock Management: PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1564

Chapter 5: Configurable Logic Blocks (CLBs)
Table 5-7: General Slice Timing Parameters
202
Combinatorial Delays
Sequential Delays
Setup and Hold Times for Slice Sequential Elements
Set/Reset
Notes:
1. This parameter includes a LUT configured as two five-input functions.
2. T
T
T
T
T
T
T
T
T
T
T
F
TOG
ILO
ILO_2
ILO_3
CKO
CKLO
DICK
CECK
SRCK
RPW
RQ
XXCK
(1)
/T
/T
/T
= Setup Time (before clock edge), and T
CKDI
CKSR
CKCE
Parameter
Timing Parameters
Table 5-7
Figure
5-25.
shows the general slice timing parameters for a majority of the paths in
A/B/C/D inputs to A/B/C/D
outputs
A/B/C/D inputs to
AMUX/CMUX outputs
A/B/C/D inputs to BMUX
output
FF Clock (CLK) to
AQ/BQ/CQ/DQ outputs
Latch Clock (CLK) to
AQ/BQ/CQ/DQ outputs
AX/BX/CX/DX inputs
CE input
SR/BY input
CKXX
Function
= Hold Time (after clock edge).
www.xilinx.com
(2)
Propagation delay from the A/B/C/D inputs of
the slice, through the look-up tables (LUTs), to the
A/B/C/D outputs of the slice (six-input
function).
Propagation delay from the A/B/C/D inputs of
the slice, through the LUTs and
F7AMUX/F7BMUX to the AMUX/CMUX
outputs (seven-input function).
Propagation delay from the A/B/C/D inputs of
the slice, through the LUTs, F7AMUX/F7BMUX,
and F8MUX to the BMUX output (eight-input
function).
Time after the clock that data is stable at the
AQ/BQ/CQ/DQ outputs of the slice sequential
elements (configured as a flip-flop).
Time after the clock that data is stable at the
XQ/YQ outputs of the slice sequential elements
(configured as a latch).
Time before/after the CLK that data from the
AX/BX/CX/DX inputs of the slice must be stable
at the D input of the slice sequential elements
(configured as a flip-flop).
Time before/after the CLK that the CE input of
the slice must be stable at the CE input of the slice
sequential elements (configured as a flip-flop).
Time before/after the CLK that the SR (Set/Reset)
and the BY (Rev) inputs of the slice must be stable
at the SR/Rev inputs of the slice sequential
elements (configured as a flip-flop).
Minimum Pulse Width for the SR (Set/Reset) and
BY (Rev) pins.
Propagation delay for an asynchronous Set/Reset
of the slice sequential elements. From the SR/BY
inputs to the AQ/BQ/CQ/DQ outputs.
Toggle Frequency – Maximum frequency that a
CLB flip-flop can be clocked: 1 / (T
Description
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
CH
+ T
CL
).