XC5VLX50T-1FFG1136C Xilinx Inc, XC5VLX50T-1FFG1136C Datasheet - Page 214

• Manufacturer Part Number: XC5VLX50T-1FFG1136C
• Description: IC FPGA VIRTEX-5 50K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG1136C

• Total Ram Bits: 2211840
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• No. Of Logic Blocks: 7200
• No. Of Gates: 50000
• Family Type: Virtex-5 LXT
• No. Of Speed Grades: 1
• No. Of I/o's: 480
• Clock Management: PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1564

Chapter 5: Configurable Logic Blocks (CLBs)
214
Other Shift Register Applications
Synchronous Shift Registers
Static-Length Shift Registers
Data Out – Q
The data output Q provides the data value (1 bit) selected by the address inputs.
Data Out – Q31 (optional)
The data output Q31 provides the last bit value of the 32-bit shift register. New data
becomes available after each shift-in operation.
Inverting Clock Pins
The clock pin (CLK) has an individual inversion option. The clock signal can be active at
the negative or positive edge of the clock without requiring other logic resources. The
default is positive clock edge.
Global Set/Reset – GSR
The global set/reset (GSR) signal does not affect the shift registers.
The shift-register primitive does not use the register available in the same slice. To
implement a fully synchronous read and write shift register, output pin Q must be
connected to a flip-flop. Both the shift register and the flip-flop share the same clock, as
shown in
X-Ref Target - Figure 5-34
This configuration provides a better timing solution and simplifies the design. Because the
flip-flop must be considered to be the last register in the shift-register chain, the static or
dynamic address should point to the desired length minus one. If needed, the cascadable
output can also be registered in a flip-flop.
The cascadable 32-bit shift register implements any static length mode shift register
without the dedicated multiplexers (F7AMUX, F7BMUX, and F8MUX).
illustrates a 72-bit shift register. Only the last SRLC32E primitive needs to have its address
inputs tied to 0b00111. Alternatively, shift register length can be limited to 71 bits
(address tied to 0b00110) and a flip-flop can be used as the last register. (In an SRLC32E
primitive, the shift register length is the address input + 1).
Address
Figure
CLK
CE
D
5-34.
Figure 5-34: Synchronous Shift Register
(Write Enable)
www.xilinx.com
SRLC32G
Q
Q31
D
FF
Q
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
UG190_5_34_050506
Synchronous
Output
Figure 5-35