XC5VLX50T-1FFG1136C Xilinx Inc, XC5VLX50T-1FFG1136C Datasheet - Page 220

• Manufacturer Part Number: XC5VLX50T-1FFG1136C
• Description: IC FPGA VIRTEX-5 50K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG1136C

• Total Ram Bits: 2211840
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• No. Of Logic Blocks: 7200
• No. Of Gates: 50000
• Family Type: Virtex-5 LXT
• No. Of Speed Grades: 1
• No. Of I/o's: 480
• Clock Management: PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1564

Chapter 6: SelectIO Resources
220
Virtex-5 FPGA Digitally Controlled Impedance (DCI)
Introduction
DCI Cascading
As FPGAs get bigger and system clock speeds get faster, PC board design and
manufacturing becomes more difficult. With ever faster edge rates, maintaining signal
integrity becomes a critical issue. PC board traces must be properly terminated to avoid
reflections or ringing.
To terminate a trace, resistors are traditionally added to make the output and/or input
match the impedance of the receiver or driver to the impedance of the trace. However, due
to increased device I/Os, adding resistors close to the device pins increases the board area
and component count, and can in some cases be physically impossible. To address these
issues and to achieve better signal integrity, Xilinx developed the Digitally Controlled
Impedance (DCI) technology.
DCI adjusts the output impedance or input termination to accurately match the
characteristic impedance of the transmission line. DCI actively adjusts the impedance of
the I/O to equal an external reference resistance. This compensates for changes in I/O
impedance due to process variation. It also continuously adjusts the impedance of the I/O
to compensate for variations of temperature and supply voltage fluctuations.
In the case of controlled impedance drivers, DCI controls the driver impedance to match
two reference resistors, or optionally, to match half the value of these reference resistors.
DCI eliminates the need for external series termination resistors.
DCI provides the parallel or series termination for transmitters or receivers. This
eliminates the need for termination resistors on the board, reduces board routing
difficulties and component count, and improves signal integrity by eliminating stub
reflection. Stub reflection occurs when termination resistors are located too far from the
end of the transmission line. With DCI, the termination resistors are as close as possible to
the output driver or the input buffer, thus, eliminating stub reflections.
Previously, using DCI I/O standards in a bank required connecting external reference
resistors to the VRN and VRP pins in that same bank. The VRN/VRP pins provide a
reference voltage used by internal DCI circuitry to adjust the I/O output impedance to
match the external reference resistors. As shown in
internally distributed throughout the bank to control the impedance of each I/O.
X-Ref Target - Figure 6-4
The Virtex-5 FPGA banks using DCI I/O standards now have the option of deriving the
DCI impedance values from another DCI bank. With DCI cascading, one bank (the master
bank) must have its VRN/VRP pins connected to external reference resistors. Also, at least
one I/O in that bank (the master bank) must be configured as DCI. Other banks in the same
column (slave banks) can use DCI standards with the same impedance as the master bank,
Local
Bank
To
www.xilinx.com
Figure 6-4: DCI Use within a Bank
DCI
Figure
6-4, a digital control bus is
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
UG190_6_95_019507
VRN/VRP