XC5VLX50T-1FFG1136C Xilinx Inc, XC5VLX50T-1FFG1136C Datasheet - Page 225

• Manufacturer Part Number: XC5VLX50T-1FFG1136C
• Description: IC FPGA VIRTEX-5 50K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG1136C

• Total Ram Bits: 2211840
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• No. Of Logic Blocks: 7200
• No. Of Gates: 50000
• Family Type: Virtex-5 LXT
• No. Of Speed Grades: 1
• No. Of I/o's: 480
• Clock Management: PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1564

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Input Termination to V
Some I/O standards require an input termination to V
X-Ref Target - Figure 6-8
DCI can also provide input termination to V
resistance is set by the reference resistors. Both GTL and HSTL standards are controlled by
50 Ω reference resistors. The DCI I/O standards supporting single termination are:
GTL_DCI, GTLP_DCI, HSTL_III_DCI, HSTL_III_DCI_18, HSTL_IV_DCI, and
HSTL_IV_DCI_18.
Figure 6-9
X-Ref Target - Figure 6-9
illustrates DCI single termination inside a Virtex-5 device.
Figure 6-9: Input Termination Using DCI Single Termination
Figure 6-8: Input Termination to V
CCO
www.xilinx.com
(Single Termination)
Z
0
Z
0
R
V
CCO
IOB
Virtex-5 DCI
V
V
REF
CCO
REF
V
CCO
SelectIO Resources General Guidelines
R
using single termination. The termination
IOB
Virtex-5 FPGA
UG190_6_07_021206
CCO
UG190_c6_06_022609
CCO
(see
without DCI
Figure
6-8).
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