XC5VLX50T-1FFG1136C Xilinx Inc, XC5VLX50T-1FFG1136C Datasheet - Page 239

• Manufacturer Part Number: XC5VLX50T-1FFG1136C
• Description: IC FPGA VIRTEX-5 50K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG1136C

• Total Ram Bits: 2211840
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• No. Of Logic Blocks: 7200
• No. Of Gates: 50000
• Family Type: Virtex-5 LXT
• No. Of Speed Grades: 1
• No. Of I/o's: 480
• Clock Management: PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1564

Specific Guidelines for I/O Supported Standards
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
LVTTL (Low Voltage Transistor-Transistor Logic)
The following subsections provide an overview of the I/O standards supported by all
Virtex-5 devices.
While most Virtex-5 FPGA I/O supported standards specify a range of allowed voltages,
this chapter records typical voltage values only. Detailed information on each specification
can be found on the Electronic Industry Alliance JEDEC web site at
The low-voltage TTL (LVTTL) standard is a general purpose EIA/JESDSA standard for
3.3V applications using an LVTTL input buffer and a push-pull output buffer. This
standard requires a 3.3V input and output supply voltage (V
use of a reference voltage (V
Sample circuits illustrating both unidirectional and bidirectional LVTTL termination
techniques are shown in
X-Ref Target - Figure 6-27
LVTTL
LVTTL
LVTTL
Figure 6-27: LVTTL Unidirectional Termination
IOB
IOB
IOB
Note: V
Figure 6-27
www.xilinx.com
REF
TT
R S = Z 0 – R D
is any voltage from 0V to V CCO
) or a termination voltage (V
R P = Z 0
Z 0
Z 0
and
Specific Guidelines for I/O Supported Standards
Z 0
V
Figure
TT
6-28.
IOB
IOB
IOB
LVTTL
LVTTL
LVTTL
CCO
TT
).
), but does not require the
http://www.jedec.org.
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