XC5VLX50T-1FFG1136C Xilinx Inc, XC5VLX50T-1FFG1136C Datasheet - Page 248

• Manufacturer Part Number: XC5VLX50T-1FFG1136C
• Description: IC FPGA VIRTEX-5 50K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG1136C

• Total Ram Bits: 2211840
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• No. Of Logic Blocks: 7200
• No. Of Gates: 50000
• Family Type: Virtex-5 LXT
• No. Of Speed Grades: 1
• No. Of I/o's: 480
• Clock Management: PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1564

Chapter 6: SelectIO Resources
248
GTL (Gunning Transceiver Logic)
GTL_DCI Usage
The Gunning Transceiver Logic (GTL) standard is a high-speed bus standard (JESD8.3)
invented by Xerox. Xilinx has implemented the terminated variation for this standard. This
standard requires a differential amplifier input buffer and an open-drain output buffer.
The negative terminal of the differential input buffer is referenced to the V
A sample circuit illustrating a valid termination technique for GTL with external parallel
termination and unconnected V
X-Ref Target - Figure 6-36
GTL does not require a V
1.2V. GTL_DCI provides single termination to V
A sample circuit illustrating a valid termination technique for GTL_DCI with internal
parallel driver and receiver termination is shown in
X-Ref Target - Figure 6-37
Table 6-13
Table 6-13: GTL DC Voltage Specifications
V
V
V
V
V
V
V
CCO
CCO
REF
TT
IH
IL
OH
Figure 6-37: GTL_DCI with Internal Parallel Driver and Receiver Termination
Figure 6-36: GTL with External Parallel Termination and Unconnected V
= V
= V
= N × V
= Unconnected
REF
REF
V
CCO
lists the GTL DC voltage specifications.
Parameter
– 0.05
+ 0.05
TT
= 1.2V
R VRP = Z 0 = 50Ω
(1)
IOB
R
P
= Z 0 = 50Ω
CCO
www.xilinx.com
IOB
voltage. However, for GTL_DCI, V
V
CCO
TT
= 1.2V
is shown in
Z 0 = 50
Min
0.74
1.14
0.79
Z 0 = 50
–
–
–
V
TT
= 1.2V
CCO
Figure
R
P
for inputs or outputs.
Figure
IOB
= Z 0 = 50Ω
V
6-36.
REF
N/A
Typ
0.83
0.77
0.8
1.2
V
–
CCO
6-37.
= 0.8V
= 1.2V
V
CCO
IOB
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
R VRP = Z 0 = 50Ω
REF
must be connected to
= 0.8V
+
–
Max
0.86
1.26
0.81
ug190_6_35_030206
–
–
-
REF
pin.
ug190_6_34_022806
+
–
CCO