XC5VLX50T-1FFG1136C Xilinx Inc, XC5VLX50T-1FFG1136C Datasheet - Page 294

• Manufacturer Part Number: XC5VLX50T-1FFG1136C
• Description: IC FPGA VIRTEX-5 50K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG1136C

• Total Ram Bits: 2211840
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• No. Of Logic Blocks: 7200
• No. Of Gates: 50000
• Family Type: Virtex-5 LXT
• No. Of Speed Grades: 1
• No. Of I/o's: 480
• Clock Management: PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1564

Chapter 6: SelectIO Resources
X-Ref Target - Figure 6-86
294
DCI
SSTL18_II_T_DCI
Differential Termination: DIFF_TERM Attribute
LVDS and Extended LVDS (Low Voltage Differential Signaling)
R 0 = 20
Ω
Figure 6-86: SSTL18_II_T_DCI (1.8V) Split-Thevenin Termination
Virtex-5 FPGA IOBs provide a 100Ω differential termination across the input differential
receiver terminals. This attribute is used in conjunction with LVDS_25, LVDSEXT_25,
HT_25, and RSDS_25. HT_25 replaces the Virtex-4 FPGA LDT_25 standard.
The on-chip input differential termination in Virtex-5 devices provides major advantages
over the external resistor by removing the stub at the receiver completely and therefore
greatly improving signal integrity:
•
•
The V
differential termination. DIFF_TERM is only available for inputs and can only be used with
a bank voltage of V
section outlines using this feature.
Low Voltage Differential Signaling (LVDS) is a very popular and powerful high-speed
interface in many system applications. Virtex-5 FPGA I/Os are designed to comply with
the EIA/TIA electrical specifications for LVDS to make system and board design easier.
With the use of an LVDS current-mode driver in the IOBs, the need for external source
termination in point-to-point applications is eliminated, and with the choice of an
extended mode, Virtex-5 devices provide the most flexible solution for doing an LVDS
design in an FPGA.
Extended LVDS provides a higher drive capability and voltage swing (350 - 750 mV),
making it ideal for long-distance or cable LVDS links. The output AC characteristics of the
LVDS extended mode driver are not within the EIA/TIA specifications. The LVDS
extended mode driver is intended for situations requiring higher drive capabilities to
produce an LVDS signal within the EIA/TIA specification at the receiver.
V
Not 3-stated
REF
Consumes less power than DCI termination
Does not use VRP/VRN pins (DCI)
= 0.9V
CCO
IOB
of the I/O bank must be connected to 2.5V ±5% to provide 100Ω of effective
CCO
Z 0
= 2.5V. The
www.xilinx.com
3-stated
IOB
V
CCO
Differential Termination Attribute
2R
2R
= 1.8V
VRP
VRN
= 2Z 0 = 100Ω
= 2Z 0 = 100Ω
V
REF
= 0.9V
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
SSTL18_II_T_DCI
ug190_6_93_041206
R 0 = 20
(DIFF_TERM)
+
–
Ω