XC5VLX50T-1FFG1136C Xilinx Inc, XC5VLX50T-1FFG1136C Datasheet - Page 3

• Manufacturer Part Number: XC5VLX50T-1FFG1136C
• Description: IC FPGA VIRTEX-5 50K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG1136C

• Total Ram Bits: 2211840
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• No. Of Logic Blocks: 7200
• No. Of Gates: 50000
• Family Type: Virtex-5 LXT
• No. Of Speed Grades: 1
• No. Of I/o's: 480
• Clock Management: PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1564

UG190 (v5.3) May 17, 2010
10/12/06
02/02/07
9/06/06
Date
Version
2.0
2.1
3.0
Added the LXT platform devices throughout document.
Chapter 1: Revised
Chapter 2: Updated
Chapter 4: Clarified the rules regarding FULL and EMPTY flags on
Chapter 5: Revised
Chapter 6:
and settings. Replaced the link to the SSO calculator.
Added System Monitor User Guide reference in the Preface.
Added XC5VLX85T to
Chapter 3: Revised
Chapter 4: Added cascade to
Removed scrub mode in
Chapter 5: Revised
Added the three SXT devices and the XC5VLX220T to
Chapter 4: Clarified wording in
Chapter 6: Added
in
Chapter 7: Revised OQ in
Chapter 8:
Table
6-39.
Differential Termination Attribute, page 237
Clock Enable Inputs - CE1 and CE2, page
DCI Cascading, page
Figure 1-22, page
Storage Elements, page
Figure
Figure 5-22, page
Output Clocks, page
www.xilinx.com
Table
Built-in Error Correction
Figure 7-27, page
3-1.
Table 4-7, page
1-5,
Synchronous Clocking, page
Table
45. Updated
197.
Revision
2-1, and
220. Changed V
65.
178.
349.
126. Revised ADDR in
Table
Clock Capable I/O, page
section.
356.
5-2.
Table
is updated for the latest syntax
REF
1-5,
for SSTL18_II_T_DCI to 0.9
119.
Virtex-5 FPGA User Guide
Table
Figure 4-9, page
page
2-1, and
139.
40.
Table
124.
5-2.