XC5VLX50T-1FFG1136C Xilinx Inc, XC5VLX50T-1FFG1136C Datasheet - Page 305

• Manufacturer Part Number: XC5VLX50T-1FFG1136C
• Description: IC FPGA VIRTEX-5 50K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG1136C

• Total Ram Bits: 2211840
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• No. Of Logic Blocks: 7200
• No. Of Gates: 50000
• Family Type: Virtex-5 LXT
• No. Of Speed Grades: 1
• No. Of I/o's: 480
• Clock Management: PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1564

Simultaneous Switching Output Limits
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Sparse-Chevron Packages
When multiple output drivers change state at the same time, power supply disturbance
occurs. These disturbances can cause undesired transient behavior in output drivers, input
receivers, or in internal logic. These disturbances are often referred to as Simultaneous-
Switching Output (SSO) noise. The SSO limits govern the number and type of I/O output
drivers that can be switched simultaneously while maintaining a safe level of SSO noise.
Virtex-5 FPGA packaging utilizes a sparse-chevron pinout arrangement. The sparse-
chevron pinout style is an improvement over previous designs, offering low crosstalk and
SSO noise. The pinout is designed to minimize PDS inductance and keep I/O signal return
current paths very closely coupled to their associated I/O signal.
The maximum ratio of I/O to reference pins (V
is 4:1. For every four I/O pins, there is always at least one reference pin.
For boards that do not meet the nominal PCB requirements listed in
Specifications, the Virtex-5 FPGA SSO calculator is available, containing all SSO limit data
for all I/O standards. For designs in nominal PCBs mixing limited and “no limit” I/O
standards, the Virtex-5 FPGA SSO calculator must be used to ensure that I/O utilization
does not exceed the limit. Information on the calculator is available under the
SSO Calculator
Unlike devices in previous families, Virtex-5 devices have only two bank sizes: 20 I/O and
40 I/O. With the ratio of signal to reference pins always constant, the SSO capacity of all
banks of 20 I/O are the same, and the capacity of all banks of 40 I/O are the same. The SSO
limits for Virtex-5 devices are listed on a per-bank basis rather than a limit per V
pair.
section.
www.xilinx.com
CCO
Simultaneous Switching Output Limits
and GND) in sparse-chevron packages
Nominal PCB
Full Device
CCO
/GND
305