XC5VLX50T-1FFG1136C Xilinx Inc, XC5VLX50T-1FFG1136C Datasheet - Page 320

• Manufacturer Part Number: XC5VLX50T-1FFG1136C
• Description: IC FPGA VIRTEX-5 50K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG1136C

• Total Ram Bits: 2211840
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• No. Of Logic Blocks: 7200
• No. Of Gates: 50000
• Family Type: Virtex-5 LXT
• No. Of Speed Grades: 1
• No. Of I/o's: 480
• Clock Management: PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1564

Chapter 7: SelectIO Logic Resources
X-Ref Target - Figure 7-2
X-Ref Target - Figure 7-3
320
CE
CE
Q1
Q2
Q1
Q2
C
D
C
D
D0A D1A D2A
D0A
Don't care
SAME_EDGE Mode
SAME_EDGE_PIPELINED Mode
D1A
In the SAME_EDGE mode, the data is presented into the FPGA fabric on the same clock
edge. However, the data pair to be separated by one clock cycle. This structure is similar to
the Virtex-II, Virtex-II Pro, and Virtex-4 FPGA implementation.
Figure 7-3
timing diagram, the output pairs Q1 and Q2 are no longer (0) and (1). Instead, the first pair
presented is pair Q1 and Q2 (0) and (don't care) respectively, followed by pair (1) and (2) on
the next clock cycle.
D0A
In the SAME_EDGE_PIPELINED mode, the data is presented into the FPGA fabric on the
same clock edge.
Unlike the SAME_EDGE mode, the data pair is not separated by one clock cycle. However,
an additional clock latency is required to remove the separated effect of the SAME_EDGE
mode.
SAME_EDGE_PIPELINED mode. The output pairs Q1 and Q2 are presented to the FPGA
fabric at the same time.
D0A
Figure 7-2: Input DDR Timing in OPPOSITE_EDGE Mode
D2A
Figure 7-3: Input DDR Timing in SAME_EDGE Mode
D1A
Figure 7-4
D3A
D3A D4A D5A D6A D7A D8A D9A D10A D11A D12A D13A
shows the timing diagram of the input DDR using SAME_EDGE mode. In the
D2A
D2A
D1A
D4A
shows the timing diagram of the input DDR using the
D3A
D5A
www.xilinx.com
D4A
D3A
D4A
D6A
D5A
D7A
D6A
D5A
D6A
D8A
D7A
D9A
D8A
D7A
D8A
D10A
D9A
D11A
Virtex-5 FPGA User Guide
D10A
D10A
UG190 (v5.3) May 17, 2010
D9A
ug190_7_02_041206
ug190_7_03_041206
D11A
D11A
D12A