XC5VLX50T-1FFG1136C Xilinx Inc, XC5VLX50T-1FFG1136C Datasheet - Page 324

• Manufacturer Part Number: XC5VLX50T-1FFG1136C
• Description: IC FPGA VIRTEX-5 50K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG1136C

• Total Ram Bits: 2211840
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• No. Of Logic Blocks: 7200
• No. Of Gates: 50000
• Family Type: Virtex-5 LXT
• No. Of Speed Grades: 1
• No. Of I/o's: 480
• Clock Management: PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1564

Chapter 7: SelectIO Logic Resources
324
Table 7-5: ILOGIC Switching Characteristics
Note:
parameters.
Setup/Hold
T
T
T
Combinatorial
T
Sequential Delays
T
T
T
T
ICE1CK
ISRCK
IDOCK
IDI
IDLO
ICKQ
ICE1Q
RQ
Symbol
The DDLY timing diagrams and parameters are identical to the D timing diagrams and
/T
/T
/T
ICKSR
IOCKD
ICKCE1
CE1 pin Setup/Hold with respect to CLK
SR/REV pin Setup/Hold with respect to CLK
D pin Setup/Hold with respect to CLK
D pin to O pin propagation delay, no Delay
D pin to Q1 pin using flip-flop as a latch without Delay
CLK to Q outputs
CE1 pin to Q1 using flip-flop as a latch, propagation delay
SR/REV pin to OQ/TQ out
www.xilinx.com
Description
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010