XC5VLX50T-1FFG1136C Xilinx Inc, XC5VLX50T-1FFG1136C Datasheet - Page 345

• Manufacturer Part Number: XC5VLX50T-1FFG1136C
• Description: IC FPGA VIRTEX-5 50K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG1136C

• Total Ram Bits: 2211840
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• No. Of Logic Blocks: 7200
• No. Of Gates: 50000
• Family Type: Virtex-5 LXT
• No. Of Speed Grades: 1
• No. Of I/o's: 480
• Clock Management: PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1564

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Output DDR Overview (ODDR)
Combinatorial Output Data and 3-State Control Path
The Output and the 3-State paths can be configured in one of the following modes
independently.
•
•
•
•
Figure 7-22
X-Ref Target - Figure 7-22
This section of the documentation discusses the various features available using the
OLOGIC resources. All connections between the OLOGIC resources are managed in Xilinx
software.
The combinatorial output paths create a direct connection from the FPGA fabric to the
output driver or output driver control. These paths is used when:
1.
2.
Virtex-5 devices have dedicated registers in the OLOGIC to implement output DDR
registers. This feature is accessed when instantiating the ODDR primitive. DDR
multiplexing is automatic when using OLOGIC. No manual control of the mux-select is
needed. This control is generated from the clock.
There is only one clock input to the ODDR primitive. Falling edge data is clocked by a
locally inverted version of the input clock. All clocks feeding into the I/O tile are fully
multiplexed, i.e., there is no clock sharing between ILOGIC or OLOGIC blocks. The ODDR
primitive supports the following modes of operation:
•
•
Edge triggered D type flip-flop
DDR mode (SAME_EDGE or OPPOSITE_EDGE)
Level Sensitive Latch
Asynchronous/combinatorial
There is direct (unregistered) connection from logic resources in the FPGA fabric to the
output data or 3-state control.
The “pack I/O register/latches into IOBs” is set to OFF.
OPPOSITE_EDGE mode
SAME_EDGE mode
illustrates the various logic resources in the OLOGIC block.
Figure 7-22: OLOGIC Block Diagram
T2
TCE
D2
OCE
T1
CLK
D1
SR
REV
www.xilinx.com
CK
CK
D1
D2
CE
D1
D2
CE
SR
SR
REV
REV
Q
Q
ug190_7_17_041206
OQ
TQ
OLOGIC Resources
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