XC5VLX50T-1FFG1136C Xilinx Inc, XC5VLX50T-1FFG1136C Datasheet - Page 346

• Manufacturer Part Number: XC5VLX50T-1FFG1136C
• Description: IC FPGA VIRTEX-5 50K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG1136C

• Total Ram Bits: 2211840
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• No. Of Logic Blocks: 7200
• No. Of Gates: 50000
• Family Type: Virtex-5 LXT
• No. Of Speed Grades: 1
• No. Of I/o's: 480
• Clock Management: PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1564

Chapter 7: SelectIO Logic Resources
346
OPPOSITE_EDGE Mode
SAME_EDGE Mode
The SAME_EDGE mode is the same as for the Virtex-4 architecture. This mode allows
designers to present both data inputs to the ODDR primitive on the rising-edge of the
ODDR clock, saving CLB and clock resources, and increasing performance. This mode is
implemented using the DDR_CLK_EDGE attribute. It is supported for 3-state control as
well. The following sections describe each of the modes in detail.
In OPPOSITE_EDGE mode, both the edges of the clock (CLK) are used to capture the data
from the FPGA fabric at twice the throughput. This structure is similar to the Virtex-II
Virtex-II Pro, and Virtex-4 FPGA implementation. Both outputs are presented to the data
input or 3-state control input of the IOB. The timing diagram of the output DDR using the
OPPOSITE_EDGE mode is shown in
X-Ref Target - Figure 7-23
In SAME_EDGE mode, data can be presented to the IOB on the same clock edge.
Presenting the data to the IOB on the same clock edge avoids setup time violations and
allows the user to perform higher DDR frequency with minimal register to register delay,
as opposed to using the CLB registers.
DDR using the SAME_EDGE mode.
X-Ref Target - Figure 7-24
OCE
OCE
Figure 7-23: Output DDR Timing in OPPOSITE_EDGE Mode
CLK
CLK
OQ
OQ
D1
D2
D1
D2
Figure 7-24: Output DDR Timing in SAME_EDGE Mode
www.xilinx.com
D1A
D1A
D2A
D1A D2A D1B
D1A D2A D1B
D2A
Figure
Figure 7-24
D1B
D1B
D2B
7-23.
D2B
D2B D1C D2C D1D
D2B D1C D2C D1D
shows the timing diagram of the output
D1C
D1C
D2C
D2C
ug190_7_18_041206
ug190_7_19_041206
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
D1D
D1D
D2D
D2D