XC5VLX50T-1FFG1136C Xilinx Inc, XC5VLX50T-1FFG1136C Datasheet - Page 359

• Manufacturer Part Number: XC5VLX50T-1FFG1136C
• Description: IC FPGA VIRTEX-5 50K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG1136C

• Total Ram Bits: 2211840
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• No. Of Logic Blocks: 7200
• No. Of Gates: 50000
• Family Type: Virtex-5 LXT
• No. Of Speed Grades: 1
• No. Of I/o's: 480
• Clock Management: PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1564

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
DATA_WIDTH Attribute
INTERFACE_TYPE Attribute
The DATA_WIDTH attribute defines the parallel data output width of the serial-to-parallel
converter. The possible values for this attribute depend on the INTERFACE_TYPE and
DATA_RATE attributes. See
Table 8-3: Recommended Data Widths
When the DATA_WIDTH is set to widths larger than six, a pair of ISERDES_NODELAY
must be configured into a master-slave configuration. See
Width expansion is not allowed in memory mode.
The INTERFACE_TYPE attribute determines whether the ISERDES_NODELAY is
configured in memory or networking mode. The allowed values for this attribute are
MEMORY or NETWORKING. The default mode is MEMORY.
When INTERFACE_TYPE is set to NETWORKING, the Bitslip submodule is available and
the OCLK port is unused. BITSLIP_ENABLE must be set to TRUE, and the Bitslip port tied
Low to disable Bitslip operation when the Bitslip module is not used in networking mode.
When set to MEMORY, the Bitslip submodule is not available (BITSLIP_ENABLE must be
set to FALSE), and the OCLK port can be used.
Figure 8-5
mode.
INTERFACE_TYPE
NETWORKING
MEMORY
illustrates the ISERDES_NODELAY internal connections when in Memory
www.xilinx.com
Table 8-3
Input Serial-to-Parallel Logic Resources (ISERDES)
for recommended data widths.
DATA_RATE
DDR
DDR
SDR
SDR
ISERDES Width
Recommended Data Widths
2, 3, 4, 5, 6, 7, 8
4, 6, 8, 10
None
4
Expansion.
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