XC5VLX50T-1FFG1136C Xilinx Inc, XC5VLX50T-1FFG1136C Datasheet - Page 362

IC FPGA VIRTEX-5 50K 1136FBGA

XC5VLX50T-1FFG1136C

Manufacturer Part Number
XC5VLX50T-1FFG1136C
Description
IC FPGA VIRTEX-5 50K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG1136C

Total Ram Bits
2211840
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Number Of I /o
480
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1136-BBGA, FCBGA
No. Of Logic Blocks
7200
No. Of Gates
50000
Family Type
Virtex-5 LXT
No. Of Speed Grades
1
No. Of I/o's
480
Clock Management
PLL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1564

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC5VLX50T-1FFG1136C
Manufacturer:
MOT
Quantity:
1 831
Part Number:
XC5VLX50T-1FFG1136C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VLX50T-1FFG1136C
Manufacturer:
XILINX
Quantity:
14
Part Number:
XC5VLX50T-1FFG1136C
Manufacturer:
XILINX
0
Part Number:
XC5VLX50T-1FFG1136C
Manufacturer:
XILINX
Quantity:
200
Part Number:
XC5VLX50T-1FFG1136C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Part Number:
XC5VLX50T-1FFG1136C
Manufacturer:
XILINX
Quantity:
8 866
Part Number:
XC5VLX50T-1FFG1136C
Quantity:
281
Part Number:
XC5VLX50T-1FFG1136C
0
Company:
Part Number:
XC5VLX50T-1FFG1136C
Quantity:
1 400
Part Number:
XC5VLX50T-1FFG1136CES
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VLX50T-1FFG1136CES
Quantity:
189
Chapter 8: Advanced SelectIO Logic Resources
362
Guidelines for Expanding the Serial-to-Parallel Converter Bit Width
X-Ref Target - Figure 8-7
1.
2.
3.
4.
5.
Both ISERDES modules must be adjacent master and slave pairs. Both ISERDES
modules must be in NETWORKING mode because width expansion is not available in
MEMORY mode.
Set the SERDES_MODE attribute for the master ISERDES to MASTER and the slave
ISERDES to SLAVE. See
The user must connect the SHIFTIN ports of the SLAVE to the SHIFTOUT ports of the
MASTER.
The SLAVE only uses the ports Q3 to Q6 as an input.
DATA_WIDTH applies to both MASTER and SLAVE in
Data Input
Figure 8-7: Block Diagram of ISERDES Width Expansion
SERDES_MODE=MASTER
D
D
SERDES_MODE=SLAVE
SHIFTOUT1 SHIFTOUT2
www.xilinx.com
SHIFTIN1
SERDES_MODE
ISERDES
ISERDES
(Master)
(Slave)
SHIFTIN2
Attribute.
Q1
Q2
Q3
Q4
Q5
Q6
Q1
Q2
Q3
Q4
Q5
Q6
Figure
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Data_internal [0:5]
Data_internal [6:9]
8-7.
ug190_8_07_100307

Related parts for XC5VLX50T-1FFG1136C