XC5VLX50T-1FFG1136C Xilinx Inc, XC5VLX50T-1FFG1136C Datasheet - Page 369

IC FPGA VIRTEX-5 50K 1136FBGA

XC5VLX50T-1FFG1136C

Manufacturer Part Number
XC5VLX50T-1FFG1136C
Description
IC FPGA VIRTEX-5 50K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG1136C

Total Ram Bits
2211840
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Number Of I /o
480
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1136-BBGA, FCBGA
No. Of Logic Blocks
7200
No. Of Gates
50000
Family Type
Virtex-5 LXT
No. Of Speed Grades
1
No. Of I/o's
480
Clock Management
PLL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1564

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC5VLX50T-1FFG1136C
Manufacturer:
MOT
Quantity:
1 831
Part Number:
XC5VLX50T-1FFG1136C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VLX50T-1FFG1136C
Manufacturer:
XILINX
Quantity:
14
Part Number:
XC5VLX50T-1FFG1136C
Manufacturer:
XILINX
0
Part Number:
XC5VLX50T-1FFG1136C
Manufacturer:
XILINX
Quantity:
200
Part Number:
XC5VLX50T-1FFG1136C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Part Number:
XC5VLX50T-1FFG1136C
Manufacturer:
XILINX
Quantity:
8 866
Part Number:
XC5VLX50T-1FFG1136C
Quantity:
281
Part Number:
XC5VLX50T-1FFG1136C
0
Company:
Part Number:
XC5VLX50T-1FFG1136C
Quantity:
1 400
Part Number:
XC5VLX50T-1FFG1136CES
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VLX50T-1FFG1136CES
Quantity:
189
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
X-Ref Target - Figure 8-13
Clock Event 4
The first two bits of the fourth word CD have been sampled into the input side registers of
the ISERDES. On this same edge of CLKDIV, the second word sampled is presented to
Q1–Q4 with one bit shifted to the right. The actual bits from the input stream that appear
at the Q1–Q4 outputs during this cycle are shown in B of
The realigned bits on Q1–Q4 are sampled into the FPGA logic on the CLKDIV domain. The
total latency from when the ISERDES captures the asserted Bitslip input to when the
realigned ISERDES outputs Q1–Q4 are sampled by CLKDIV is two CLKDIV cycles.
Clock Event 5
The third word sampled is presented to Q1–Q4 with three bits shifted to the left. The actual
bits from the input stream that appear at the Q1–Q4 outputs during this cycle are shown in
C of
Figure
C
A
B
8-13.
Q1–Q4 During Clock Event 3
(No Bitslip)
Q1–Q4 During Clock Event 4
(1st Bitslip, Rotate 1 Bit to Right)
Q1–Q4 During Clock Event 5
(2nd Bitslip, Rotate 3 Bits to Left)
Figure 8-13: Bits from Data Input Stream (D) of
www.xilinx.com
Input Serial-to-Parallel Logic Resources (ISERDES)
C D A B C D
C D A B C D
C D A B C D
Figure
A B C D A B
A B C D A B
A B C D A B
8-13.
Figure 8-12
ug190_c8_13_100307
C D
C D
C D
369

Related parts for XC5VLX50T-1FFG1136C