XC5VLX50T-1FFG1136C Xilinx Inc, XC5VLX50T-1FFG1136C Datasheet - Page 383

• Manufacturer Part Number: XC5VLX50T-1FFG1136C
• Description: IC FPGA VIRTEX-5 50K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG1136C

• Total Ram Bits: 2211840
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• No. Of Logic Blocks: 7200
• No. Of Gates: 50000
• Family Type: Virtex-5 LXT
• No. Of Speed Grades: 1
• No. Of I/o's: 480
• Clock Management: PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1564

Index
A
asynchronous
B
Bitslip
block RAM
BLVDS
BUFG
BUFGCE
BUFGCTRL
BUFGMUX
BUFGMUX_CTRL
BUFIO
BUFR
C
CLB
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
clocking
distributed RAM
global set/reset
mux
set/reset in register or latch
See ISERDES
guidelines for use
operation
timing
defined
asynchronous clocking
ECC
ECC Port
operating modes
ports
synchronous clocking
with CE
array size by device
distributed RAM
maximum distributed RAM
number of flip-flops
number of LUTs by device
number of shift registers
register/latch configuration
173
42
31
366
41
296
Primitive
NO_CHANGE
READ_FIRST
WRITE_FIRST
32
36
158
125
368
115
33
28
37
119
162
366
353
35
161
127
181
180
367
118
118
118
177
177
119
119
177
177
180
177
179
CLK2X
CLKDV
CLKFB
CLKFX
clock capable I/O
clock forwarding
clock regions
clock tree
clocking wizard
clocks
CMT
combinatorial input path
configuration
D
DCI
DCLK
DCM
DDR
delay element
slice description
SLICEL
SLICEM
global clock buffers
I/O clock buffer
regional clock buffers
regions
resources
allocation in device
DCM
defined
allocation in device
attributes
clock deskew
clocking wizard
configuration
DCM_ADV
DCM_BASE
design guidelines
deskew
dynamic reconfiguration
frequency synthesis
output ports
phase shifting
ports
timing models
IDDR
220
47
48
53
55
52
55
55
38
51
65
319
220
www.xilinx.com
38
174
67
39
174
29
58
83
51
,
347
50
54
40
61
48
65
49
84
,
83
174
41
,
63
63
68
48
48
26
49
,
319
85
40
,
,
27
67
,
49
42
,
73
Differential
differential termination
E
Error Correction Code (ECC)
F
FIFO
G
GCLK
global clocks
GSR
GTL
H
HSTL
See IDELAY
HSTL Class II
HSTL Class II (1.8V)
LVPECL
SSTL Class II (1.8V)
SSTL2 Class II (2.5V)
DIFF_TERM
attributes
cascading
FWFT mode
operating modes
ports
primitive
standard mode
status flags
timing parameters
clock buffers
clock I/O inputs
defined
defined
GTL_DCI
GTLP
GTLP_DCI
defined
class I
class I (1.8V)
class II
248
139
250
38
143
249
252
250
127
248
250
254
297
142
147
248
157
249
145
325
144
237
263
25
256
144
,
,
,
26
26
144
294
274
149
294
286
264
277
,
,
158
291
,
267
281
383