XC5VLX50T-1FFG1136C Xilinx Inc, XC5VLX50T-1FFG1136C Datasheet - Page 40

• Manufacturer Part Number: XC5VLX50T-1FFG1136C
• Description: IC FPGA VIRTEX-5 50K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG1136C

• Total Ram Bits: 2211840
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• No. Of Logic Blocks: 7200
• No. Of Gates: 50000
• Family Type: Virtex-5 LXT
• No. Of Speed Grades: 1
• No. Of I/o's: 480
• Clock Management: PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1564

Chapter 1: Clock Resources
Regional Clocking Resources
40
Clock Capable I/O
Regional clock networks are a set of clock networks independent of the global clock
network. Unlike global clocks, the span of a regional clock signal (BUFR) is limited to three
clock regions, while the I/O clock signal drives a single region only. These networks are
especially useful for source-synchronous interface designs. The I/O banks in Virtex-5
devices are the same size as a clock region.
To understand how regional clocking works, it is important to understand the signal path
of a regional clock signal. The regional clocking resources and network in Virtex-5 devices
consist of the following paths and components:
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•
•
•
In a typical clock region there are four clock-capable I/O pin pairs (there are exceptions in
the center column). Clock-capable I/O pairs are regular I/O pairs in select locations with
special hardware connections to nearby regional clock resources. Some global clock inputs
are also clock-capable I/Os. There are four dedicated clock-capable I/O sites in every
bank. When used as clock inputs, clock-capable pins can drive BUFIO and BUFR. Clock-
capable I/Os in the center column can not drive BUFRs. Clock-capable I/Os can not
directly connect to the global clock buffers. When used as single-ended clock pins, then as
described in
connection only exists on this pin.
Clock Capable I/O
I/O Clock Buffer - BUFIO
Regional Clock Buffer - BUFR
Regional Clock Nets
Global Clock
www.xilinx.com
Buffers, the P-side of the pin pair must be used because a direct
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010