XC5VLX50T-1FFG1136C Xilinx Inc, XC5VLX50T-1FFG1136C Datasheet - Page 57

IC FPGA VIRTEX-5 50K 1136FBGA

XC5VLX50T-1FFG1136C

Manufacturer Part Number
XC5VLX50T-1FFG1136C
Description
IC FPGA VIRTEX-5 50K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG1136C

Total Ram Bits
2211840
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Number Of I /o
480
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1136-BBGA, FCBGA
No. Of Logic Blocks
7200
No. Of Gates
50000
Family Type
Virtex-5 LXT
No. Of Speed Grades
1
No. Of I/o's
480
Clock Management
PLL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1564

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC5VLX50T-1FFG1136C
Manufacturer:
MOT
Quantity:
1 831
Part Number:
XC5VLX50T-1FFG1136C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VLX50T-1FFG1136C
Manufacturer:
XILINX
Quantity:
14
Part Number:
XC5VLX50T-1FFG1136C
Manufacturer:
XILINX
0
Part Number:
XC5VLX50T-1FFG1136C
Manufacturer:
XILINX
Quantity:
200
Part Number:
XC5VLX50T-1FFG1136C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Part Number:
XC5VLX50T-1FFG1136C
Quantity:
281
Part Number:
XC5VLX50T-1FFG1136C
0
Company:
Part Number:
XC5VLX50T-1FFG1136C
Quantity:
1 400
Part Number:
XC5VLX50T-1FFG1136CES
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VLX50T-1FFG1136CES
Quantity:
189
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Dynamic Reconfiguration Ready Output - DRDY
Table 2-4: DCM Status Mapping to DO Bus (Continued)
When LOCKED is Low (during reset or the locking process), all the status signals are
deasserted Low.
The dynamic reconfiguration ready (DRDY) output pin provides the response to the DEN
signal for the DCM’s dynamic reconfiguration feature. Further information on the DRDY
pin is available in the dynamic reconfiguration section in the Virtex-5 FPGA Configuration
Guide.
DO[3]
DO[15:4]
DO Bit
CLKFB stopped
Not assigned
Status
www.xilinx.com
Asserted when the feedback clock is stopped (CLKFB
remains High or Low for one or more clock cycles). The
DO[3] CLKFB stopped status is asserted within six
CLKIN cycles after CLKFB is stopped. CLKFB stopped
will deassert within six CLKIN cycles when CLKFB
resumes after being stopped momentarily. An
occasionally skipped CLKFB does not affect the DCM
operation. However, stopping CLKFB for a long time
can result in the DCM losing LOCKED. When LOCKED
is lost, the DCM needs to be reset to resume operation.
When the DLL portion of the DCM is not used (for
example, when using CLKFX output only), the CLKFB
can be left unconnected. In this case, DO[3] is
deasserted.
Description
DCM Ports
57

Related parts for XC5VLX50T-1FFG1136C