XC5VLX50T-1FFG1136C Xilinx Inc, XC5VLX50T-1FFG1136C Datasheet - Page 59

• Manufacturer Part Number: XC5VLX50T-1FFG1136C
• Description: IC FPGA VIRTEX-5 50K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG1136C

• Total Ram Bits: 2211840
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• No. Of Logic Blocks: 7200
• No. Of Gates: 50000
• Family Type: Virtex-5 LXT
• No. Of Speed Grades: 1
• No. Of I/o's: 480
• Clock Management: PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1564

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
CLKIN_DIVIDE_BY_2 Attribute
CLKOUT_PHASE_SHIFT Attribute
CLK_FEEDBACK Attribute
The CLKIN_DIVIDE_BY_2 attribute is used to enable a toggle flip-flop in the input clock
path to the DCM. When set to FALSE, the effective CLKIN frequency of the DCM equals
the source clock frequency driving the CLKIN input. When set to TRUE, the CLKIN
frequency is divided by two before it reaches the rest of the DCM. Thus, the DCM sees half
the frequency applied to the CLKIN input and operates based on this frequency. For
example, if a 100 MHz clock drives CLKIN, and CLKIN_DIVIDE_BY_2 is set to TRUE;
then the effective CLKIN frequency is 50 MHz. Thus, CLK0 output is 50 MHz and CLK2X
output is 100 MHz. The effective CLKIN frequency must be used to evaluate any operation
or specification derived from CLKIN frequency. The possible values for
CLKIN_DIVIDE_BY_2 are TRUE and FALSE. The default value is FALSE.
The CLKOUT_PHASE_SHIFT attribute indicates the mode of the phase shift applied to the
DCM outputs. The possible values are NONE, FIXED, VARIABLE_POSITIVE,
VARIABLE_CENTER, or DIRECT. The default value is NONE.
When set to NONE, a phase shift cannot be performed and a phase-shift value has no effect
on the DCM outputs. When set to FIXED, the DCM outputs are phase-shifted by a fixed
phase from the CLKIN. The phase-shift value is determined by the PHASE_SHIFT
attribute. If the CLKOUT_PHASE_SHIFT attribute is set to FIXED or NONE, then the
PSEN, PSINCDEC, and the PSCLK inputs must be tied to ground.
When set to VARIABLE_POSITIVE, the DCM outputs can be phase-shifted in variable
mode in the positive range with respect to CLKIN. When set to VARIABLE_CENTER, the
DCM outputs can be phase-shifted in variable mode, in the positive and negative range
with respect to CLKIN. If set to VARIABLE_POSITIVE or VARIABLE_CENTER, each
phase-shift increment (or decrement) increases (or decreases) the phase shift by a period of
1/256 x CLKIN period.
When set to DIRECT, the DCM output can be phase-shifted in variable mode in the
positive range with respect to CLKIN. Each phase-shift increment/decrement will
increase/decrease the phase shift by one DCM_TAP. See the Virtex-5 FPGA Data Sheet.
The starting phase in the VARIABLE_POSITIVE and VARIABLE_CENTER modes is
determined by the phase-shift value. The starting phase in the DIRECT mode is always
zero, regardless of the value specified by the PHASE_SHIFT attribute. Thus, the
PHASE_SHIFT attribute should be set to zero when DIRECT mode is used. A non-zero
phase-shift value for DIRECT mode can be loaded to the DCM using Dynamic
Reconfiguration Ports in the Virtex-5 FPGA Configuration Guide.
The CLK_FEEDBACK attribute determines the type of feedback applied to the CLKFB.
The possible values are 1X or NONE. The default value is 1X. When set to 1X, CLKFB pin
must be driven by CLK0. When set to NONE leave the CLKFB pin unconnected.
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DCM Attributes
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