XC5VLX50T-1FFG1136C Xilinx Inc, XC5VLX50T-1FFG1136C Datasheet - Page 62

• Manufacturer Part Number: XC5VLX50T-1FFG1136C
• Description: IC FPGA VIRTEX-5 50K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG1136C

• Total Ram Bits: 2211840
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• No. Of Logic Blocks: 7200
• No. Of Gates: 50000
• Family Type: Virtex-5 LXT
• No. Of Speed Grades: 1
• No. Of I/o's: 480
• Clock Management: PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1564

Chapter 2: Clock Management Technology
Table 2-6: DCM Attributes (Continued)
62
CLKOUT_PHASE_SHIFT
DESKEW_ADJUST
DFS_FREQUENCY_MODE
DLL_FREQUENCY_MODE
DUTY_CYCLE_CORRECTION
DCM_PERFORMANCE_MODE
FACTORY_JF
PHASE_SHIFT
STARTUP_WAIT
DCM Attribute Name
This attribute specifies the phase-
shift mode.
This affects the amount of delay in
the feedback path, and should be
used for source-synchronous
interfaces.
This specifies the frequency mode of
the frequency synthesizer.
This specifies the frequency mode of
the DLL.
This controls the DCM 1X outputs
(CLK0, CLK90, CLK180, and
CLK270), to exhibit a 50/50 duty
cycle. Leave this attribute set at the
default value.
Allows selection between maximum
frequency/ minimum jitter, and low
frequency/maximum phase-shift
range
DLL_FREQUENCY_MODE=LOW
default (0x
DLL_FREQUENCY_MODE=HIGH
default (0x
This specifies the phase-shift
numerator. The value range
depends on
CLKOUT_PHASE_SHIFT and clock
frequency.
When this attribute is set to TRUE,
the configuration startup sequence
waits in the specified cycle until the
DCM locks.
F0F0
F0F0)
Description
).
.
www.xilinx.com
String: NONE or FIXED or
VARIABLE_POSITIVE or
VARIABLE_CENTER or
DIRECT
String:
SYSTEM_SYNCHRONOUS
or
SOURCE_SYNCHRONOUS
String: LOW or HIGH
String: LOW or HIGH
Boolean: TRUE or FALSE
String: MAX_SPEED or
MAX_RANGE
BIT_VECTOR
Integer: –255 to 1023
Boolean: FALSE or TRUE
Values
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
NONE
SYSTEM_
SYNCHRONOUS
LOW
LOW
TRUE
MAX_SPEED
0xF0F0
0
FALSE
Default Value