XC5VLX50T-1FFG1136C Xilinx Inc, XC5VLX50T-1FFG1136C Datasheet - Page 68

• Manufacturer Part Number: XC5VLX50T-1FFG1136C
• Description: IC FPGA VIRTEX-5 50K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG1136C

• Total Ram Bits: 2211840
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• No. Of Logic Blocks: 7200
• No. Of Gates: 50000
• Family Type: Virtex-5 LXT
• No. Of Speed Grades: 1
• No. Of I/o's: 480
• Clock Management: PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1564

Chapter 2: Clock Management Technology
68
Phase Shifting
Frequency Synthesizer Characteristics
Phase-Shifting Operation
Only when feedback is provided to the CLKFB input of the DCM is the frequency
synthesizer output phase aligned to the clock output, CLK0.
The internal operation of the frequency synthesizer is complex and beyond the scope of
this document. As long as the frequency synthesizer is within the range specified in the
Virtex-5 FPGA Data Sheet, it multiplies the incoming frequencies by the pre-calculated
quotient M ÷ D and generates the correct output frequencies.
For example, assume an input frequency of 50 MHz, M = 25, and D = 8 (M and D values do
not have common factors and cannot be reduced). The output frequency is 156.25 MHz
although separate calculations, 25 x 50 MHz = 1.25 GHz and 50 MHz ÷ 8 = 6.25 MHz,
seem to produce separate values outside the range of the input frequency.
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The DCM provides coarse and fine-grained phase shifting. For coarse-phase control, the
CLK0, CLK90, CLK180, and CLK270 outputs are each phase-shifted by ¼ of the input clock
period relative to each other. Similarly, CLK2X180 and CLKFX180 provide a 180° coarse
phase shift of CLK2X and CLKFX, respectively. The coarse phase-shifted clocks are
produced from the delay lines of the DLL circuit. The phase relationship of these clocks is
retained when CLKFB is not connected.
Fine-grained phase shifting uses the CLKOUT_PHASE_SHIFT and PHASE_SHIFT
attributes to phase-shift DCM output clocks relative to CLKIN. Since the CLKIN is used as
the reference clock, the feedback (CLKFB) connection is required for the phase-shifting
circuit to compare the incoming clock with the phase-shifted clock. The rest of this section
describes fine-grained phase shifting in the Virtex-5 FPGA DCM.
All nine DCM output clocks are adjusted when fine-grained phase shifting is activated.
The phase shift between the rising edges of CLKIN and CLKFB is a specified fraction of the
input clock period or a specific amount of DCM_TAP. All other DCM output clocks retain
their phase relation to CLK0.
Phase-Shift Range
The allowed phase shift between CLKIN and CLKFB is limited by the phase-shift range.
There are two separate phase-shift ranges:
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The frequency synthesizer provides an output frequency equal to the input frequency
multiplied by M and divided by D.
The outputs CLKFX and CLKFX180 always have a 50/50 duty-cycle.
Smaller M and D values achieve faster lock times. Whenever possible, divide M and D
by the largest common factor to get the smallest values. (e.g., if the required
CLKFX = 9/6 x CLKIN, instead of using M = 9 and D = 6, use M = 3 and D = 2.)
When CLKFB is connected, CLKFX is phase aligned with CLK0 every D cycles of
CLK0 and every M cycles of CLKFX if M/D is a reduced fraction.
PHASE_SHIFT attribute range
FINE_SHIFT_RANGE DCM timing parameter range
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010