XC5VLX50T-1FFG1136C Xilinx Inc, XC5VLX50T-1FFG1136C Datasheet - Page 99

• Manufacturer Part Number: XC5VLX50T-1FFG1136C
• Description: IC FPGA VIRTEX-5 50K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG1136C

• Total Ram Bits: 2211840
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• No. Of Logic Blocks: 7200
• No. Of Gates: 50000
• Family Type: Virtex-5 LXT
• No. Of Speed Grades: 1
• No. Of I/o's: 480
• Clock Management: PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1564

Table 3-4: PLL Attributes (Continued)
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
DIVCLK_DIVIDE
CLKFBOUT_PHASE
REF_JITTER
CLKIN1_PERIOD
CLKIN2_PERIOD
CLKOUT[0:5]_
DESKEW_ADJUST
RESET_ON_LOSS
_OF_LOCK
Attribute
Integer
String
String
Type
Real
Real
Real
Real
Allowed Values
1.408 to 52.630
1.408 to 52.630
0.000 to 0.999
PPC or None
0.0 to 360.0
FALSE
1 to 52
www.xilinx.com
Default
FALSE
None
0.100
0.000
0.000
0.0
1
Specifies the division ratio for all
output clocks with respect to the
input clock.
Specifies the phase offset in
degrees of the clock feedback
output. Shifting the feedback clock
results in a negative phase shift of
all output clocks to the PLL.
Allows specification of the
expected jitter on the reference
clock in order to better optimize
PLL performance. A bandwidth
setting of OPTIMIZED will
attempt to choose the best
parameter for input clocking
when unknown. If known, then
the value provided should be
specified in terms of the UI
percentage (the maximum peak to
peak value) of the expected jitter
on the input clock.
Specifies the input period in ns to
the PLL CLKIN1 input. Resolution
is down to the ps. This information
is mandatory and must be
supplied.
Specifies the input period in ns to
the PLL CLKIN2 input. Resolution
is down to the ps. This information
is mandatory and must be
supplied.
Fixed delay used when the PLL is
used in a PPC440 system.
See UG200: Embedded Processor
Block in Virtex-5 FPGAs Reference
Guide for details.
Must be set to FALSE, not
supported in silicon.
General Usage Description
Description
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