XC5VLX50T-1FFG1136C Xilinx Inc, XC5VLX50T-1FFG1136C Datasheet - Page 83

IC FPGA VIRTEX-5 50K 1136FBGA

XC5VLX50T-1FFG1136C

Manufacturer Part Number
XC5VLX50T-1FFG1136C
Description
IC FPGA VIRTEX-5 50K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG1136C

Total Ram Bits
2211840
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Number Of I /o
480
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1136-BBGA, FCBGA
No. Of Logic Blocks
7200
No. Of Gates
50000
Family Type
Virtex-5 LXT
No. Of Speed Grades
1
No. Of I/o's
480
Clock Management
PLL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1564
Source-Synchronous Switching Characteristics
The parameters in this section provide the necessary values for calculating timing budgets for Virtex-5 FPGA
source-synchronous transmitter and receiver data-valid windows.
Table 98: Duty Cycle Distortion and Clock-Tree Skew
DS202 (v5.3) May 5, 2010
Product Specification
Notes:
1.
2.
T
T
T
T
T
DCD_CLK
CKSKEW
DCD_BUFIO
BUFIOSKEW
DCD_BUFR
These parameters represent the worst-case duty cycle distortion observable at the pins of the device using LVDS output buffers. For cases
where other I/O standards are used, IBIS can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical
rise/fall times.
The T
skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor
and Timing Analyzer tools to evaluate clock skew specific to the application.
Symbol
CKSKEW
value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree
Global Clock Tree Duty Cycle Distortion
Global Clock Tree Skew
I/O clock tree duty cycle distortion
I/O clock tree skew across one clock region
Regional clock tree duty cycle distortion
Description
(2)
www.xilinx.com
(1)
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
XC5VLX20T
XC5VLX30
XC5VLX30T
XC5VLX50
XC5VLX50T
XC5VLX85
XC5VLX85T
XC5VLX110
XC5VLX110T
XC5VLX155
XC5VLX155T
XC5VLX220
XC5VLX220T
XC5VLX330
XC5VLX330T
XC5VSX35T
XC5VSX50T
XC5VSX95T
XC5VSX240T
XC5VTX150T
XC5VTX240T
XC5VFX30T
XC5VFX70T
XC5VFX100T
XC5VFX130T
XC5VFX200T
Device
All
All
All
All
0.12
0.21
0.21
0.26
0.26
0.42
0.42
0.48
0.48
0.82
0.82
0.38
0.43
0.34
0.41
0.82
0.82
0.10
0.07
0.25
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
-3
Speed Grade
0.12
0.24
0.22
0.22
0.27
0.27
0.43
0.43
0.50
0.50
0.85
0.85
1.07
1.07
1.25
1.25
0.39
0.44
0.72
1.32
0.70
0.97
0.35
0.42
0.84
0.84
1.24
0.10
0.07
0.25
-2
0.12
0.25
0.22
0.22
0.28
0.28
0.45
0.45
0.51
0.51
0.88
0.88
1.10
1.10
1.29
1.29
0.39
0.45
0.74
1.36
0.73
1.00
0.35
0.43
0.86
0.86
1.29
0.10
0.08
0.25
-1
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
83

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