XC5VLX50T-1FFG1136C Xilinx Inc, XC5VLX50T-1FFG1136C Datasheet - Page 85

IC FPGA VIRTEX-5 50K 1136FBGA

XC5VLX50T-1FFG1136C

Manufacturer Part Number
XC5VLX50T-1FFG1136C
Description
IC FPGA VIRTEX-5 50K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG1136C

Total Ram Bits
2211840
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Number Of I /o
480
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1136-BBGA, FCBGA
No. Of Logic Blocks
7200
No. Of Gates
50000
Family Type
Virtex-5 LXT
No. Of Speed Grades
1
No. Of I/o's
480
Clock Management
PLL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1564
Table 100: Sample Window
Table 101: Source-Synchronous Pin-to-Pin Setup/Hold and Clock-to-Out
Revision History
The following table shows the revision history for this document.
DS202 (v5.3) May 5, 2010
Product Specification
Notes:
1.
2.
T
T
Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO
T
Pin-to-Pin Clock-to-Out Using BUFIO
T
SAMP
SAMP_BUFIO
PSCS
ICKOFCS
04/14/06
05/12/06
05/24/06
08/04/06
This parameter indicates the total sampling error of Virtex-5 FPGA DDR input registers across voltage, temperature, and process. The
characterization methodology uses the DCM to capture the DDR input registers’ edges of operation. These measurements include:
- CLK0 DCM jitter
- DCM accuracy (phase offset)
- DCM phase shift resolution
These measurements do not include package or clock tree skew.
This parameter indicates the total sampling error of Virtex-5 FPGA DDR input registers across voltage, temperature, and process. The
characterization methodology uses the BUFIO clock network and IODELAY to capture the DDR input registers’ edges of operation. These
measurements do not include package or clock tree skew.
Date
Symbol
/T
PHCS
Symbol
Version
1.0
1.1
1.2
1.3
Sampling Error at Receiver Pins
Sampling Error at Receiver Pins using BUFIO
Setup/Hold of I/O clock
Clock-to-Out of I/O clock
Initial Xilinx release.
• First version posted to the Xilinx website. Minor typographical edits. Revised design software version on
• Revised T
• Revised TDSPCKO in
Added register-to-register parameters to
• Added V
• Added HSTL_I_12 and LVCMOS12 to
• Removed pin-to-pin performance (Table 12). Updated and added values to register-register
• Added values to
• Updated the speed specification version above
• Added to
• Revised F
• In
• Removed Note 2 on
page
performance
SSTL18_II_T_DCI.
pointing to Architecture Wizard.
Table
30.
74, changed F
DRINT
Table 56
IDELAYRESOLUTION
MAX
Description
Table 52
, V
values in
DRI
Table
the I/O standards: HSTL_II_T_DCI, HSTL_II_T_DCI_18, SSTL2_II_T_DCI, and
, and C
Table
(1)
(was Table 13).
Table 69, page
53.
VCOMAX
Description
Table
88.
IN
www.xilinx.com
in
values to
68, and RDWR_B Setup/Hold values in
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
, removed T
Table 64, page
(2)
Table
48.
Table 7
Table
LOCKMIN
52.
Revision
3.
44.
and renumbered the notes.
Table
Device
All
All
, and revised T
54.
450
350
-3
–0.56
LOCKMAX
1.59
4.42
-3
Speed Grade
Table
Speed Grade
500
400
values, also removed note
-2
–0.54
70.
1.72
4.82
-2
550
450
–0.54
1.91
5.40
-1
-1
Units
Units
ps
ps
ns
ns
85

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