XC5VLX50T-2FF1136C Xilinx Inc, XC5VLX50T-2FF1136C Datasheet - Page 87

IC FPGA VIRTEX-5 50K 1136FBGA

XC5VLX50T-2FF1136C

Manufacturer Part Number
XC5VLX50T-2FF1136C
Description
IC FPGA VIRTEX-5 50K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr

Specifications of XC5VLX50T-2FF1136C

Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
2211840
Number Of I /o
480
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1136-BBGA, FCBGA
For Use With
122-1586 - BOARD EVAL FOR VIRTEX-5 ML555HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC5VLX50T-2FF1136C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VLX50T-2FF1136C
Manufacturer:
XILINX
Quantity:
200
Part Number:
XC5VLX50T-2FF1136C
Quantity:
220
DS202 (v5.3) May 5, 2010
Product Specification
02/02/07
Date
Version
3.0
• Added XC5VSX35T, XC5VSX50T, and SX5VSX95T devices to appropriate tables.
• Revised the I
• Revised the I
• Added values to
• Minor added notes and changed descriptions in
• Revised the SFI-4.1 (SDR LVDS Interface) -1 values in
• Revised gain error, bipolar gain error, and event conversion time in
• Changed the design software version that matches this data sheet above
• In
• In
• In
• Revised values in
• LVCMOS25, Fast, 12 mA in
• Setup and Hold and T
• T
• Sequential delay values in
• T
• T
• T
• T
• T
• T
• Parameters in
• Revised values in
• Clarified description in
• Revised values in
• Removed duplicate T
Switching
Virtex-5 Device Pin-to-Pin Output Parameter
Virtex-5 Device Pin-to-Pin Input Parameter
T
F
OCKQ
CXB
RCKO_DO
RCCK_WREN
DSPDCK_CC
MAX_MULT_NOMREG_PATDET
BCCKO_O
BUFIOCKO_O
BRCKO_O
, T
in
CEO
Table 61, page
Characteristics, the following values are revised:
RPU
CCAUXQ
, and T
, T
and T
, and T
, T
RCKO_POINTERS
, and T
Table 5, page
and F
values in
Table 74, page 55
DSPCCK_{RSTAA, RSTBB}
Table 101, page
BRCKO_O_BYP
BGCKO_O
Table
Table
values in
DICK
MAX
RCO_FLAGS
BUFR_MAX_FREQ
ICKQ
Table 91, page
in
Table 3, page
in
www.xilinx.com
84,
91,
41.
Table 65, page
in
Table 72, page
Table 63, page
in
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Table 4, page
6.
Table
Table
Table 56, page
, T
in
Table 71, page
Table 60, page
in
RCKO_ECCR
Table 69, page
in
85.
Table 73, page
including notes.
Table 68, page
85, and
92, and
, T
and T
2.
69.
DSPCKO_{PP, CRYOUTP}
44.
Revision
53.
3.
43.
, T
Table
Table
Guidelines:
32.
BUFIO_MAX_FREQ
53.
Guidelines:
RCKO_ECC
40.
Table 25, page 13
48.
86.
93.
54.
47.
Table 53, page
, T
RCCK_ADDR
from
, F
and
Table 51, page 26
MAX_MULT_NOMREG
Table
29.
Table 26, page
, T
Table 54
RDCK_DI
98.
, T
on
RDCK_DI_ECC
page
13.
and
30.
,
87

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