XC5VLX50T-2FFG665I Xilinx Inc, XC5VLX50T-2FFG665I Datasheet - Page 128

IC FPGA VIRTEX-5 50K 665FCBGA

XC5VLX50T-2FFG665I

Manufacturer Part Number
XC5VLX50T-2FFG665I
Description
IC FPGA VIRTEX-5 50K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr

Specifications of XC5VLX50T-2FFG665I

Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
2211840
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
665-BBGA, FCBGA
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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Chapter 4: Block RAM
Block RAM Address Mapping
Table 4-8: Port Address Mapping
Block RAM Attributes
128
Width
16 + 2
32 + 4
8 + 1
Port
1
2
4
Locations
3 2 1 0
1
Parity
N.A.
0
Content Initialization - INIT_xx
0
3
1
15
3
0
7
Each port accesses the same set of 18,432 or 36,864 memory cells using an addressing
scheme dependent on whether it is a RAMB18 or RAMB36. The physical RAM locations
addressed for a particular width are determined using the following formula (of interest
only when the two ports use different aspect ratios):
Table 4-8
All attribute code examples are discussed in the
Verilog Code
Additional RAMB18 and RAMB36 Primitive Design Considerations
INIT_xx attributes define the initial memory contents. By default, block RAM memory is
initialized with all zeros during the device configuration sequence. The 64 initialization
attributes from INIT_00 through INIT_3F for the RAMB18, and the 128 initialization
attributes from INIT_00 through INIT_7F for the RAMB36 represent the regular memory
contents. Each INIT_xx is a 64-digit hex-encoded bit vector. The memory contents can be
partially initialized and are automatically completed with zeros.
The following formula is used for determining the bit positions for each INIT_xx attribute.
Given yy = conversion hex-encoded to decimal (xx), INIT_xx corresponds to the memory
cells as follows:
For example, for the attribute INIT_1F, the conversion is as follows:
More examples are given in
2
9
14
2
8
END = ((ADDR + 1)
START = ADDR
from [(yy + 1) × 256] – 1
to (yy) × 256
yy = conversion hex-encoded to decimal (xx) “1F” = 31
from [(31+1) × 256] – 1 = 8191
to 31 × 256 = 7936
3
2
7
13
shows low-order address mapping for each port width.
2
6
6
section. Further information on using these attributes is available in the
2
5
12
2
4
1
×
2
3
11
Width
2
2
www.xilinx.com
5
Table
×
2
1
10
Width) -1
2
0
4-9.
Data Locations
2
1
9
9
1
8
0
4
1
7
8
1
6
Block RAM Initialization in VHDL or
1
5
7
1
4
3
1
3
6
1
2
1
11
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
5
1
0
section.
2
0
9 8 7 6 5 4 3 2 1 0
4
3
1
2
0
1
0
0

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