XC5VLX50T-2FFG665I Xilinx Inc, XC5VLX50T-2FFG665I Datasheet - Page 149

• Manufacturer Part Number: XC5VLX50T-2FFG665I
• Description: IC FPGA VIRTEX-5 50K 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-2FFG665I

• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 2211840
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 665-BBGA, FCBGA
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

FIFO VHDL and Verilog Templates
FIFO Timing Models and Parameters
Table 4-20: FIFO Timing Parameters
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Setup and Hold Relative to Clock (CLK)
T
T
T
T
T
T
T
T
Clock to Out Delays
T
T
T
T
T
T
T
RXCK
RCKX
RDCK_DI
RCKD_DI
RCCK_RDEN
RCKC_RDEN
RCCK_WREN
RCKC_WREN
RCKO_DO
RCKO_AEMPTY
RCKO_AFULL
RCKO_EMPTY
RCKO_FULL
RCKO_RDERR
RCKO_WRERR
Parameter
= Setup time (before clock edge)
= Hold time (after clock edge)
/
(4)
(1)
(2)
/
(5)
/
(5)
(2)
(2)
(2)
(2)
(2)
Data inputs
Read enable
Write enable
Clock to data output
Clock to almost empty
output
Clock to almost full
output
Clock to empty output
Clock to full output
Clock to read error
output
Clock to write error
output
Similarly, the ALMOST_EMPTY flag can be used to stop reading. However, this would
make it impossible to read the very last entries remaining in the FIFO. The user can ignore
the Almost Empty signal and continue to read until EMPTY is asserted.
The Almost Full and Almost Empty offsets can also be used in unstoppable block transfer
applications to signal that a complete block of data can be written or read.
When setting the offset ranges in the design tools, use hexadecimal notation.
VHDL and Verilog templates are available in the Libraries Guide.
Table 4-20
Function
shows the FIFO parameters.
AEMPTY
WRERR
Control
EMPTY
www.xilinx.com
AFULL
RDERR
WREN
Signal
RDEN
FULL
DO
DI
Time before/after RDCLK that RDEN must be stable.
Time before/after WRCLK that WREN must be stable.
Time after RDCLK that the output data is stable at the
DO outputs of the FIFO. The synchronous FIFO with
DO_REG = 0 is different than in multirate mode.
Time after RDCLK that the Almost Empty signal is
stable at the ALMOSTEMPTY outputs of the FIFO.
Time after WRCLK that the Almost Full signal is
stable at the ALMOSTFULL outputs of the FIFO.
Time after RDCLK that the Empty signal is stable at
the EMPTY outputs of the FIFO.
Time after WRCLK that the Full signal is stable at the
FULL outputs of the FIFO.
Time after RDCLK that the Read Error signal is stable
at the RDERR outputs of the FIFO.
Time after WRCLK that the Write Error signal is stable
at the WRERR outputs of the FIFO.
Time before/after WRCLK that D1 must be stable.
FIFO VHDL and Verilog Templates
Description
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