XC5VLX50T-2FFG665I Xilinx Inc, XC5VLX50T-2FFG665I Datasheet - Page 154

• Manufacturer Part Number: XC5VLX50T-2FFG665I
• Description: IC FPGA VIRTEX-5 50K 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-2FFG665I

• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 2211840
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 665-BBGA, FCBGA
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 4: Block RAM
154
Case 3: Reading From a Full FIFO
Prior to the operations performed in
X-Ref Target - Figure 4-23
Clock Event 1 and Clock Event 2: Read Operation and Deassertion of Full Signal
During a read operation on a full FIFO, the content of the FIFO at the first address is
asserted at the DO output pins of the FIFO. Two RDEN operations ensure that the FIFO is
no longer full, and after three WRCLK cycles the FULL pin is deasserted.
The example in
are with respect to read-clock. Clock event 4 appears three write-clock cycles after clock
event 2.
•
•
•
If the rising RDCLK edge is close to the rising WRCLK edge, FULL could be deasserted one
WRCLK period later.
Clock Event 3 and Clock Event 5: Read Operation and Deassertion of Almost
FULL Signal
Three write-clock cycles after the fourth data is read from the FIFO, the Almost FULL pin
is deasserted to signify that the FIFO is not in the almost FULL state.
The example in
respect to read-clock, while clock event 5 is with respect to write-clock. Clock event 5
appears three write-clock cycles after clock event 3.
•
•
WRCLK
RDCLK
WREN
AFULL
RDEN
FULL
At time T
RDEN input of the FIFO.
At time T
outputs of the FIFO.
At time T
Read enable remains asserted at the RDEN input of the FIFO.
At time T
AFULL pin.
DO
FCCK_RDEN
FCKO_DO
FCKO_FULL
FCKO_AFULL
1
Figure 4-23
Figure 4-23
T
FCCK_RDEN
00
, after clock event 1 (RDCLK), data 00 becomes valid at the DO
T
2
Figure 4-23: Reading From a Full FIFO
, after clock event 4 (WRCLK), FULL is deasserted.
FCKO_DO
, before clock event 1 (RDCLK), read enable becomes valid at the
, after clock event 5 (RDCLK), Almost FULL is deasserted at the
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reflects both standard and FWFT modes. Clock event 3 is with
reflects both standard and FWFT modes. Clock event 1 and 2
01
Figure
02
3
4-23, the FIFO is completely full.
4
03
T
FCKO_FULL
04
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
5
05
T
ug190_4_19_040606
FCKO_AFULL
06