XC5VLX50T-2FFG665I Xilinx Inc, XC5VLX50T-2FFG665I Datasheet - Page 156

• Manufacturer Part Number: XC5VLX50T-2FFG665I
• Description: IC FPGA VIRTEX-5 50K 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-2FFG665I

• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 2211840
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 665-BBGA, FCBGA
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 4: Block RAM
156
Case 5: Resetting All Flags
Clock Event 3: Read Operation and Assertion of Read Error Signal
The read error signal pin is asserted when there is no data to be read because the FIFO is in
an empty state.
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Clock Event 4: Read Operation and Deassertion of Read Error Signal
The read error signal pin is deasserted when a user stops trying to read from an empty
FIFO.
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The read error signal is asserted/deasserted at every read-clock positive edge. As long as
both the read enable and empty signals are true, read error will remain asserted.
X-Ref Target - Figure 4-25
When the reset signal is asserted, all flags are reset.
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•
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Reset is an asynchronous signal used to reset all flags. Hold the reset signal High for three
read and write clock cycles to ensure that all internal states and flags are reset to the correct
value.
Read enable remains asserted at the RDEN input of the FIFO.
At time T
RDERR output pin of the FIFO.
Data 04 remains unchanged at the DO outputs of the FIFO.
At time T
RDEN input of the FIFO.
At time T
RDERR output pin of the FIFO.
At time T
the FIFO.
At time T
output pin of the FIFO.
At time T
FIFO.
At time T
pin of the FIFO.
AEMPTY
WRCLK
EMPTY
RDCLK
AFULL
FULL
RST
FCKO_RDERR
FCCK_RDEN
FCKO_RDERR
FCO_EMPTY
FCO_AEMPTY
FCO_FULL
FCO_AFULL
, after reset (RST), full is deasserted at the FULL output pin of the
, after reset (RST), empty is asserted at the EMPTY output pin of
, after reset (RST), almost full is deasserted at the AFULL output
, before clock event 4 (RDCLK), read enable is deasserted at the
, after reset (RST), almost empty is asserted at the AEMPTY
, after clock event 3 (RDCLK), read error is asserted at the
, after clock event 4 (RDCLK), read error is deasserted at the
www.xilinx.com
Figure 4-25: Resetting All Flags
T
T
T
T
FCO_EMPTY
FCO_AEMPTY
FCO_FULL
FCO_AFULL
ug190_4_22_032506
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010