XC5VLX50T-2FFG665I Xilinx Inc, XC5VLX50T-2FFG665I Datasheet - Page 234

IC FPGA VIRTEX-5 50K 665FCBGA

XC5VLX50T-2FFG665I

Manufacturer Part Number
XC5VLX50T-2FFG665I
Description
IC FPGA VIRTEX-5 50K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr

Specifications of XC5VLX50T-2FFG665I

Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
2211840
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
665-BBGA, FCBGA
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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Chapter 6: SelectIO Resources
234
OBUFT
IOBUF
IBUFDS and IBUFGDS
The generic 3-state output buffer OBUFT, shown in
3-state outputs or bidirectional I/O.
X-Ref Target - Figure 6-20
The IOBUF primitive is needed when bidirectional signals require both an input buffer and
a 3-state output buffer with an active High 3-state pin.
FPGA IOBUF.
X-Ref Target - Figure 6-21
The usage and rules corresponding to the differential primitives are similar to the single-
ended SelectIO primitives. Differential SelectIO primitives have two pins to and from the
device pads to show the P and N channel pins in a differential pair. N channel pins have a
“B” suffix.
Figure 6-22
X-Ref Target - Figure 6-22
Figure 6-22: Differential Input Buffer Primitive (IBUFDS/IBUFGDS)
shows the differential input buffer primitive
Figure 6-20: 3-State Output Buffer (OBUFT) Primitive
Figure 6-21: Input/Output Buffer (IOBUF) Primitive
3-state input
from FPGA
O (Output)
3-state input
From FPGA
to FPGA
I (Input)
www.xilinx.com
I (Input)
T
device pads
Inputs from
T
IB
I
IOBUF
IBUFDS/IBUFGDS
OBUFT
+
ug190_6_20_022806
Figure
O
Figure 6-21
I/O
to/from device pad
Output to
FPGA
O (Output)
to device pad
ug190_6_18_022806
ug190_6_19_022806
6-20, typically implements
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
shows a generic Virtex-5

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