XC5VLX50T-2FFG665I Xilinx Inc, XC5VLX50T-2FFG665I Datasheet - Page 275

• Manufacturer Part Number: XC5VLX50T-2FFG665I
• Description: IC FPGA VIRTEX-5 50K 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-2FFG665I

• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 2211840
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 665-BBGA, FCBGA
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
SSTL2_I, SSTL18_I
SSTL2_I_DCI, SSTL18_I_DCI
SSTL2_II, SSTL18_II
SSTL2_II_DCI, SSTL18_II_DCI
DIFF_SSTL2_I, DIFF_SSTL18_I
DIFF_SSTL2_I_DCI, DIFF_SSTL18_I_DCI
DIFF_SSTL2_II, DIFF_SSTL18_II
DIFF_SSTL2_II_DCI, DIFF_SSTL18_II_DCI
SSTL2_II_T_DCI, SSTL18_II_T_DCI
Class I signaling uses V
the receiver. A series resistor (25 Ω at 2.5V, 20 Ω at 1.8V) must be connected to the
transmitter output.
The DCI transmitter provides the internal series resistance (25 Ω at 2.5V, 20 Ω at 1.8V). The
DCI receiver has an internal split thevenin termination powered from V
equivalent V
Class II signaling uses V
the receiver and transmitter respectively. A series resistor (25 Ω at 2.5V, 20 Ω at 1.8V) must
be connected to the transmitter output for a unidirectional link. For a bidirectional link,
25 Ω series resistors must connected the transmitters of the transceivers.
The DCI circuits have a split thevenin termination powered from V
series resistor (25 Ω at 2.5V, 20 Ω at 1.8V). For a unidirectional link the internal series
resistance is supplied only for the transmitter. A bidirectional link has the internal series
resistor for both transmitters.
Differential SSTL 2.5V and 1.8V Class I pairs complementary single-ended SSTL_I type
drivers with a differential receiver.
Differential SSTL 2.5V and 1.8V Class I pairs complementary single-ended SSTL_II type
drivers with a differential receiver, including on-chip differential split thevenin
termination.
Differential SSTL 2.5V and 1.8V Class II pairs complementary single-ended SSTL_II type
drivers with a differential receiver. For a bidirectional link, a series resistor must be
connected to both transmitters.
Differential SSTL 2.5V and 1.8V Class II pairs complementary single-ended SSTL_II type
drivers with a differential receiver, including on-chip differential termination. DCI can be
used for unidirectional and bidirectional links.
SSTL2_II_T_DCI and SSTL18_II_T_DCI provide on-chip split thevenin termination
powered from V
standards are 3-stated. When not 3-stated, these two standards do not have parallel
termination but when invoked they have an internal series resistor (25 Ω at 2.5V and
20 Ω at 1.8V.)
TT
voltage and termination impedance.
CCO
that creates an equivalent termination voltage of V
TT
TT
www.xilinx.com
(V
(V
CCO
CCO
/2) as a parallel termination voltage to a 50 Ω resistor at
/2) as a parallel termination voltage to a 50 Ω resistor at
Specific Guidelines for I/O Supported Standards
CCO
CCO
CCO
and an internal
/2 when these
creating an
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