XC5VLX50T-2FFG665I Xilinx Inc, XC5VLX50T-2FFG665I Datasheet - Page 302

• Manufacturer Part Number: XC5VLX50T-2FFG665I
• Description: IC FPGA VIRTEX-5 50K 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-2FFG665I

• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 2211840
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 665-BBGA, FCBGA
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 6: SelectIO Resources
302
3.3V I/O Design Guidelines
I/O Standard Design Rules
To achieve maximum performance in Virtex-5 devices, several 3.3V I/O design guidelines
and techniques are highlighted in this section. This includes managing
overshoot/undershoot with termination techniques, regulating V
voltage regulator, using external bus switches, reviewing configuration methods, and
other design considerations.
Overshoot/Undershoot
Undershoot and overshoot voltages on I/Os operating at 3.3V should not exceed the
absolute maximum ratings of –0.3V to 4.05V, respectively, when V
absolute maximum limits are stated in the absolute maximum ratings table in the Virtex-5
FPGA Data Sheet. However, the maximum undershoot value is directly affected by the
value of V
The voltage across the gate oxide at any time must not exceed 4.05V. Consider the case in
which the I/O is either an input or a 3-stated buffer as shown in
output PMOS transistor P
ground, respectively.
The amount of undershoot allowed without overstressing the PMOS transistor P
gate voltage minus the gate oxide limit, or V
Similarly, the absolute maximum overshoot allowed without overstressing the NMOS
transistor N
X-Ref Target - Figure 6-91
The clamp diodes offer protection against transient voltage beyond approximately
V
the current going through it. Therefore the clamped level is not fixed and can vary
CCO
+ 0.5V and Ground – 0.5V. The voltage across the diode increases proportionally to
P
N
Output Driver
CCO
o
o
0
is the gate voltage plus the gate oxide limit, or Ground + 4.05V.
V
.
CCO
Figure 6-91: Virtex-5 FPGA I/O: 3-State Output Driver
D
D
G
www.xilinx.com
0
P
Ground
Clamp
Clamp
Power
Diode
Diode
and NMOS transistor N
GND
External
Pin
CCO
– 4.05V.
0
is connected essentially to V
Input Buffer
V
CCO
N
P
Figure
i
i
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
CCO
CCO
6-91. The gate of the
at 3.0V with a
is 3.75V. These
GND
ug190_6_85_030506
0
CCO
is the
and