XC5VLX50T-2FFG665I Xilinx Inc, XC5VLX50T-2FFG665I Datasheet - Page 319

• Manufacturer Part Number: XC5VLX50T-2FFG665I
• Description: IC FPGA VIRTEX-5 50K 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-2FFG665I

• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 2211840
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 665-BBGA, FCBGA
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Combinatorial Input Path
Input DDR Overview (IDDR)
OPPOSITE_EDGE Mode
Table 7-2: Truth Table when SRVAL = 1
The SRVAL attributes can be set individually for each storage element in the ILOGIC block,
but the choice of synchronous or asynchronous set/reset (SRTYPE) can not be set
individually for each storage element in the ILOGIC block.
The following sections discuss the various resources within the ILOGIC blocks. All
connections between the ILOGIC resources are managed in Xilinx software.
The combinatorial input path is used to create a direct connection from the input driver to
the FPGA fabric. This path is used by software automatically when:
1.
2.
Virtex-5 devices have dedicated registers in the ILOGIC to implement input double-data-
rate (DDR) registers. This feature is used by instantiating the IDDR primitive.
There is only one clock input to the IDDR primitive. Falling edge data is clocked by a
locally inverted version of the input clock. All clocks feeding into the I/O tile are fully
multiplexed, i.e., there is no clock sharing between ILOGIC and OLOGIC blocks. The
IDDR primitive supports the following modes of operation:
•
•
•
The SAME_EDGE and SAME_EDGE_PIPELINED modes are the same as for the Virtex-4
architecture. These modes allow designers to transfer falling edge data to the rising edge
domain within the ILOGIC block, saving CLB and clock resources, and increasing
performance. These modes are implemented using the DDR_CLK_EDGE attribute. The
following sections describe each of the modes in detail.
A traditional input DDR solution, or OPPOSITE_EDGE mode, is accomplished via a single
input in the ILOGIC. The data is presented to the fabric via the output Q1 on the rising
edge of the clock and via the output Q2 on the falling edge of the clock. This structure is
similar to the Virtex-II, Virtex-II Pro, and Virtex-4 FPGA implementation.
the timing diagram of the input DDR using the OPPOSITE_EDGE mode.
SR
0
0
1
1
There is a direct (unregistered) connection from input data to logic resources in the
FPGA fabric.
The "pack I/O register/latches into IOBs" is set to OFF.
OPPOSITE_EDGE mode
SAME_EDGE mode
SAME_EDGE_PIPELINED mode
REV
0
1
0
1
NOP
Set
Reset
Reset
www.xilinx.com
Function
ILOGIC Resources
Figure 7-2
shows
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