XC5VLX50T-2FFG665I Xilinx Inc, XC5VLX50T-2FFG665I Datasheet - Page 330

• Manufacturer Part Number: XC5VLX50T-2FFG665I
• Description: IC FPGA VIRTEX-5 50K 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-2FFG665I

• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 2211840
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 665-BBGA, FCBGA
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 7: SelectIO Logic Resources
330
IODELAY Timing
ODELAY_VALUE Attribute
The ODELAY_VALUE attribute specifies tap delays. The possible values are any integer
from 0 to 63. The default value is zero. The value of the tap delay reverts to
ODELAY_VALUE when the tap delay is reset.
HIGH_PERFORMANCE_MODE Attribute
When TRUE, this attribute reduces the output jitter. This reduction results in a slight
increase in power dissipation from the IODELAY element. When set to FALSE the
IODELAY element consumes less power.
SIGNAL_PATTERN Attribute
Clock and data signals have different electrical profiles and therefore accumulate different
amounts of jitter in the IODELAY chain. By setting the SIGNAL_PATTERN attribute, the
user enables timing analyzer to account for jitter appropriately when calculating timing. A
clock signal is periodic in nature and does not have long sequences of consecutive ones or
zeroes, while data is random in nature and can have long and short sequences of ones and
zeroes.
Table 7-11
Table 7-11: IODELAY Switching Characteristics
Figure 7-9
X-Ref Target - Figure 7-9
T
T
T
T
IDELAYRESOLUTION
ICECK
IINCCK
IRSTCK
DATAOUT
/T
/T
/T
RST
INC
CE
shows the IODELAY switching characteristics.
ICKCE
shows an IDELAY timing diagram. It is assumed that IDELAY_VALUE = 0.
ICKINC
ICKRST
C
Symbol
Figure 7-9: IDELAY Timing Diagram
www.xilinx.com
1
Tap 0
IDELAY tap resolution
CE pin Setup/Hold with respect to C
INC pin Setup/Hold with respect to C
RST pin Setup/Hold with respect to C
2
3
Tap 1
Description
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
UG190_7_09_100107