XC5VLX50T-2FFG665I Xilinx Inc, XC5VLX50T-2FFG665I Datasheet - Page 347

• Manufacturer Part Number: XC5VLX50T-2FFG665I
• Description: IC FPGA VIRTEX-5 50K 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-2FFG665I

• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 2211840
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 665-BBGA, FCBGA
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Output DDR Primitive (ODDR)
Clock Forwarding
Output DDR can forward a copy of the clock to the output. This is useful for propagating
a clock and DDR data with identical delays, and for multiple clock generation, where every
clock load has a unique clock driver. This is accomplished by tying the D1 input of the
ODDR primitive High, and the D2 input Low. Xilinx recommends using this scheme to
forward clocks from the FPGA fabric to the output pins.
Figure 7-25
signals.
ODDR primitive.
X-Ref Target - Figure 7-25
Table 7-13: ODDR Port Signals
Table 7-14: ODDR Attributes
Q
C
CE
D1 and D2
R
S
DDR_CLK_EDGE
INIT
SRTYPE
Attribute Name
Name
Port
Table 7-14
shows the ODDR primitive block diagram.
Data output (DDR)
Clock input port
Clock enable port
Data inputs
Reset
Set
describes the various attributes available and default values for the
Function
Figure 7-25: ODDR Primitive Block Diagram
Sets the ODDR mode of operation with
respect to clock edge
Sets the initial value for Q port
Set/Reset type with respect to clock (C)
www.xilinx.com
CE
D1
D2
C
ODDR register output.
The CLK pin represents the clock input pin.
CE represents the clock enable pin. When asserted Low,
this port disables the output clock on port Q.
ODDR register inputs.
Synchronous/Asynchronous reset pin. Reset is asserted
High.
Synchronous/Asynchronous set pin. Set is asserted
High.
Description
S
R
ODDR
ug190_7_20_012207
Table 7-13
Description
Q
OPPOSITE_EDGE
(default), SAME_EDGE
0 (default), 1
ASYNC, SYNC (default)
lists the ODDR port
Possible Values
OLOGIC Resources
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