XC5VLX50T-2FFG665I Xilinx Inc, XC5VLX50T-2FFG665I Datasheet - Page 350

• Manufacturer Part Number: XC5VLX50T-2FFG665I
• Description: IC FPGA VIRTEX-5 50K 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-2FFG665I

• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 2211840
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 665-BBGA, FCBGA
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 7: SelectIO Logic Resources
350
Clock Event 9
At time T
synchronous reset in this case) becomes valid-High resetting ODDR register, reflected at
the OQ output at time T
and resetting ODDR register, reflected at the OQ output at time T
(no change at the OQ output in this case).
Figure 7-28
X-Ref Target - Figure 7-28
Clock Event 1
•
•
Clock Event 2
•
Figure 7-29
in opposite edge mode. For other modes add the appropriate latencies as shown in
Figure 7-4, page
CLK
TCE
SR
TQ
T1
At time T
High at the TCE input of the 3-state register, enabling the 3-state register for incoming
data.
At time T
input of the 3-state register, returning the pad to high-impedance at time T
Clock Event 1.
At time T
in this case) becomes valid-High, resetting the 3-state register at time T
Event 2.
OSRCK
T
OCKQ
illustrates the OLOGIC 3-state register timing.
Figure 7-28: OLOGIC 3-State Register Timing Characteristics
illustrates IOB DDR 3-state register timing. This example is shown using DDR
OTCECK
OTCK
OSRCK
before Clock Event 9 (rising edge of CLK), the SR signal (configured as
321.
1
before Clock Event 1 the 3-state signal becomes valid-High at the T
before Clock Event 2, the SR signal (configured as synchronous reset
before Clock Event 1, the 3-state clock enable signal becomes valid-
T
T
OTCK
OTCECK
RQ
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after Clock Event 9 (no change at the OQ output in this case)
2
T
OSRCK
T
RQ
3
4
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
RQ
after Clock Event 10
RQ
UG190_7_23_041106
5
after Clock
OCKQ
after