XC5VLX50T-2FFG665I Xilinx Inc, XC5VLX50T-2FFG665I Datasheet - Page 4

IC FPGA VIRTEX-5 50K 665FCBGA

XC5VLX50T-2FFG665I

Manufacturer Part Number
XC5VLX50T-2FFG665I
Description
IC FPGA VIRTEX-5 50K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr

Specifications of XC5VLX50T-2FFG665I

Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
2211840
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
665-BBGA, FCBGA
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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XC5VLX50T-2FFG665I
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Virtex-5 FPGA User Guide
09/11/07
Date
Version
3.1
Chapter 1: Added
Revised
Chapter 2: Revised DCM reset and locking process in
Updated DO[2] description in
page
Clocks, page
Added more steps to
values on
Figure 2-20, page
Chapter 3: Updated
to
CLKFBIN, CLKFBDCM, CLKFBOUT, RST, LOCKED, and added the REL pin and note 2
to
page
Missing Input Clock or Feedback Clock
Corrected the Virtex-4 port mapping in
Chapter 4: Revised and clarified
Clarified Readback limitation in
Set/Reset - SSR[A|B], page
latency values and added Note 1 to
Increase Depth, page
Chapter 5: Clarified information about common control signals in a slice in
Elements, page
Chapter 6: Updated the DCI cascading guidelines on
“HSLVDCI Controlled Impedance Driver with Unidirectional Termination” since it is
not supported in software. Added note 3 to
introduction to
DIFF_SSTL2_II_DCI, DIFF_SSTL18_II_DCI, page
in
the Same Bank, page
Overshoot/Undershoot, page
Chapter 7: Removed DDLY port from IDDR primitive
_PATTERN, DELAY_SRC, and REFCLK_FREQUENCY attributes to
page
Clock From DCM” and updated REFCLK section in
Clarified introduction in
Forwarding, page
Chapter 8: Updated SR and O in
section for
page
Figure 6-74, page
Phase Shift, page
Table 3-3, page
58. Revised the description for
98. Removed general routing discussion from
329. Revised
370.
Figure 1-16, page
page
BITSLIP Submodule, page
65, updated
73. Updated
SSTL (Stub-Series Terminated Logic), page
178.
87.
96. Added RESET_ON_LOSS_OF_LOCK attribute to
Clock Gating for Power Savings, page
Figure 7-9, page
347.
95. Added rounding to
282. Revised rules 2 and 3 in
Figure 3-1, page
www.xilinx.com
298. Deleted of absolute maximum table from
Dynamic Reconfiguration
157.
IDELAYCTRL Locations, page
Figure 2-7, page
37.
125. Added
Figure 2-7, page
302.
Table 2-4, page
Built-in Error
Simple Dual-Port Block RAM, page
Figure 8-2
330. Removed Table 7-12: “Generating Reference
Table 4-16, page
FACTORY_JF Attribute, page
90. Add notes to
366. Fixed typographical errors in
Revision
Figure 3-17
section. Added waveforms to
Block RAM Retargeting, page
74, and added a BUFG to Figure 2-10, page 72.
Equation 3-3
and
Table 6-17, page
74. Revised bulleted descriptions under
Correction. Edited WE signal throughout.
56. Changed the multiply value range on
(DRPs) when loading new M and D
Table 8-1, page
Rules for Combining I/O Standards in
275. Fixed DIFF_SSTL2_II references
PLL Clock Input
and
IDELAYCTRL Ports, page
145. Updated
page
Reset Input - RST, page
Table 3-2, page
page
Table 3-8, page
26. Revised
339. Changed ODDR
through
223. Removed references to
274. Revised
321. Added the SIGNAL
256. Clarified the
UG190 (v5.3) May 17, 2010
355. Updated the entire
Equation
61. Revised
Cascading FIFOs to
Figure 1-2, page
Table 7-10,
Signals. Revised
121. Edited
93. Added a note
Figure
139. Revised
Table 3-4,
111.
Figure 8-14,
3-6. Revised
Storage
3-13.
Clock
53.
Output
338.
30.

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