XC5VLX50T-2FFG665I Xilinx Inc, XC5VLX50T-2FFG665I Datasheet - Page 5

• Manufacturer Part Number: XC5VLX50T-2FFG665I
• Description: IC FPGA VIRTEX-5 50K 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-2FFG665I

• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 2211840
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 665-BBGA, FCBGA
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

UG190 (v5.3) May 17, 2010
02/05/08
03/31/08
04/25/08
12/11/07
Date
Version
3.2
3.3
4.0
4.1
Chapter 1: Revised description in
XC5VLX20T, XC5VLX155, and XC5VLX155T devices to
Chapter 2: Added the XC5VLX20T, XC5VLX155, and XC5VLX155T devices to
Chapter 3: Revised
descriptions of CLKFBOUT and DEN in
CLKOUT[0:5]_PHASE and CLKFBOUT_MULT description in
Revised
Chapter 5: Added the XC5VLX20T, XC5VLX155, and XC5VLX155T devices to
Chapter 6: Clarified discussion of cascading across CMT tiles in
Changed the split termination to V
Chapter 7: Added to the descriptions of the
and the
description in
Chapter 8: Complete rewrite of the chapter. Many changes to descriptions, tables, and
figures.
Chapter 1: Updated discussion under
Chapter 3: Revised LOCKED description in
Detailed VCO and Output Counter Waveforms, page
Chapter 5: Updated description of
Chapter 7: Updated description under
to TRUE for HIGH_PERFORMANCE_MODE in
Chapter 8: Revised TRISTATE_WIDTH in
under
page
Added the FXT platform to
Revised timing event description under
Revised
Added CLKOUT[0:5]_DESKEW_ADJUST to
Corrected READ_WIDTH_B = 9 to WRITE_WIDTH_B = 9 in the block RAM usage rules
on
Revised
Corrected BITSLIP_ENABLE value from string to boolean in
Attributes, page
Added the XC5VSX240T to
Revised
Removed a pad notation from the ODDR output of
Removed the BUFG on the output of Figure 2-10.
Updated CLKOUT[0:5]_DESKEW_ADJUST description in
Revised equations
Updated the notes in
Revised description of
page
page
375.
342.
TRISTATE_WIDTH Attribute
SIGNAL_PATTERN Attribute, page
Figure 3-13
Dynamic Reconfiguration, page 73
114.
High-Speed Clock for Strobe-Based Memory Interfaces - OCLK, page
Figure 1-21, page
Instantiating IDELAYCTRL Without LOC Constraints, page
358.
Equation 3-5
Clock Network Deskew, page
and
www.xilinx.com
Table 4-16, page
Instantiating IDELAYCTRL with Location (LOC) Constraints,
Figure 3-14
44.
Table
Table
and
1-5,
1-5,
Clock Gating for Power Savings, page
TT
Figure
and added section on
including waveforms.
Equation
Table
Table
I/O Clock Buffer - BUFIO, page
145.
= 0.9V in
Clock Input - C, page
Revision
Figure 1-21, page
Table 3-3, page
5-17.
Table 8-7, page
Table 3-3, page
HIGH_PERFORMANCE_MODE
2-1, and
2-1, and
to remove adjustment of PHASE_SHIFT.
330,including
Table 3-4, page
3-6.
Figure 6-84, page
Table 7-10, page
93. Removed note 2 and revised
Figure
Table
Table
103.
Table
96. Revised allowed value of
OSERDES Clocking Methods,
374. Updated discussion
44.
5-2.
5-2.
96. Revised discussion under
2-9.
Table
Table 3-4, page
327. Updated default value
98.
ISERDES_NODELAY
1-5.
Virtex-5 FPGA User Guide
Table 3-4, page
DCI
7-10. Revised
292.
329.
Cascading.
41.
26. Added the
98.
340.
Attribute,
98.
Table
Table
357.
2-1.
5-2.