XC5VLX50T-2FFG665I Xilinx Inc, XC5VLX50T-2FFG665I Datasheet - Page 52

IC FPGA VIRTEX-5 50K 665FCBGA

XC5VLX50T-2FFG665I

Manufacturer Part Number
XC5VLX50T-2FFG665I
Description
IC FPGA VIRTEX-5 50K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr

Specifications of XC5VLX50T-2FFG665I

Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
2211840
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
665-BBGA, FCBGA
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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Chapter 2: Clock Management Technology
52
Feedback Clock Input - CLKFB
Phase-Shift Clock Input - PSCLK
The feedback clock (CLKFB) input pin provides a reference or feedback signal to the DCM
to delay-compensate the clock outputs, and align them with the clock input. To provide the
necessary feedback to the DCM, connect only the CLK0 DCM output to the CLKFB pin.
When the CLKFB pin is connected, all clock outputs are deskewed to CLKIN. When the
CLKFB pin is not connected, DCM clock outputs are not deskewed to CLKIN. However,
the relative phase relationship between all output clocks is preserved.
During internal feedback configuration, the CLK0 output of a DCM connects to a global
buffer on the same top or bottom half of the device. The output of the global buffer
connects to the CLKFB input of the same DCM.
During the external feedback configuration, the following rules apply:
1.
2.
Figure 2-9
The feedback clock input signal can be driven by one of the following buffers:
1.
2.
3.
The phase-shift clock (PSCLK) input pin provides the source clock for the DCM phase
shift. The PSCLK can be asynchronous (in phase and frequency) to CLKIN. The phase-shift
clock signal can be driven by any clock source (external or internal), including:
1.
2.
3.
4.
The frequency range of PSCLK is defined by PSCLK_FREQ_LF/HF. See the Virtex-5 FPGA
Data Sheet. This input must be tied to ground when the CLKOUT_PHASE_SHIFT attribute
is set to NONE or FIXED.
To forward the clock, the CLK0 of the DCM must directly drive an OBUF or a BUFG-
to-DDR configuration.
External to the FPGA, the forwarded clock signal must be connected to the IBUFG
(GCLK pin) or the IBUF driving the CLKFB of the DCM. Both CLK and CLKFB should
have identical I/O buffers.
IBUFG – Global Clock Input Buffer
This is the preferred source for an external feedback configuration. When an IBUFG
drives a CLKFB pin of a DCM in the same top or bottom half of the device, the pad to
DCM skew is compensated for deskew.
BUFGCTRL – Internal Global Clock Buffer
This is an internal feedback configuration driven by CLK0.
IBUF – Input Buffer
This is an external feedback configuration. When IBUF is used, the PAD to DCM input
skew is not compensated and performance can not be guaranteed.
IBUF – Input Buffer
IBUFG – Global Clock Input Buffer
To access the dedicated routing, only the IBUFGs on the same half of the device (top or
bottom) as the DCM can be used to drive a PSCLK input of the DCM.
BUFGCTRL – An Internal Global Buffer
Internal Clock – Any internal clock using general purpose routing.
illustrates clock forwarding with external feedback configuration.
www.xilinx.com
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010

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