XC5VLX50T-2FFG665I Xilinx Inc, XC5VLX50T-2FFG665I Datasheet - Page 56

• Manufacturer Part Number: XC5VLX50T-2FFG665I
• Description: IC FPGA VIRTEX-5 50K 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-2FFG665I

• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 2211840
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 665-BBGA, FCBGA
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 2: Clock Management Technology
56
DCM Status and Data Output Ports
Locked Output - LOCKED
Phase-Shift Done Output - PSDONE
Status or Dynamic Reconfiguration Data Output - DO[15:0]
The LOCKED output indicates whether the DCM clock outputs are valid, i.e., the outputs
exhibit the proper frequency and phase. After a reset, the DCM samples several thousand
clock cycles to achieve lock. After the DCM achieves lock, the LOCKED signal is asserted
High. The DCM timing parameters section of the Virtex-5 FPGA Data Sheet provides
estimates for locking times.
To guarantee an established system clock at the end of the start-up cycle, the DCM can
delay the completion of the device configuration process until after the DCM is locked. The
STARTUP_WAIT attribute activates this feature. The
description provides further information.
Until the LOCKED signal is asserted High, the DCM output clocks are not valid and can
exhibit glitches, spikes, or other spurious movement. In particular, the CLK2X output
appears as a 1x clock with a 25/75 duty cycle.
The phase-shift done (PSDONE) output signal is synchronous to PSCLK. At the
completion of the requested phase shift, PSDONE pulses High for one period of PSCLK.
This signal also indicates a new change to the phase shift can be initiated. The PSDONE
output signal is not valid if the phase-shift feature is not being used or is in fixed mode.
The DO output bus provides DCM status or data output when using dynamic
reconfiguration
available in the Dynamic Reconfiguration chapter of the Virtex-5 FPGA Configuration Guide
for more information.
If the dynamic reconfiguration port is not used, using DCM_BASE instead of DCM_ADV
is strongly recommended.
Table 2-4: DCM Status Mapping to DO Bus
DO[0]
DO[1]
DO[2]
DO Bit
Phase-shift overflow
CLKIN stopped
CLKFX stopped
(Table
Status
2-4). Further information on using DO as the data output is
www.xilinx.com
Asserted when the DCM is phase-shifted beyond the
allowed phase-shift value or when the absolute delay
range of the phase-shift delay line is exceeded. DO[0] is
deasserted if the phase shift feature is not used
(CLKOUT_PHASE_SHIFT=NONE).
Asserted when the input clock is stopped (CLKIN
remains High or Low for one or more clock cycles).
When CLKIN is stopped, the DO[1] CLKIN stopped
status is asserted within nine CLKIN cycles. When
CLKIN is restarted, CLK0 starts toggling and DO[1] is
deasserted within nine clock cycles.
Asserted when CLKFX stops. The DO[2] CLKFX
stopped status is asserted within 260 cycles after
CLKFX stopped. CLKFX does not resume, and DO[2] is
not deasserted until the DCM is reset. DO[2] is
deasserted if the CLKFX/CLKFX180 output is not used.
STARTUP_WAIT Attribute
Description
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010