XC5VLX50T-2FFG665I Xilinx Inc, XC5VLX50T-2FFG665I Datasheet - Page 71

• Manufacturer Part Number: XC5VLX50T-2FFG665I
• Description: IC FPGA VIRTEX-5 50K 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-2FFG665I

• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 2211840
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 665-BBGA, FCBGA
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

X-Ref Target - Figure 2-6
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
PSINCDEC
PSDONE
PSCLK
PSEN
Interaction of PSEN, PSINCDEC, PSCLK, and PSDONE
DCM_TAP. Changing the ratio of V
proportional to the size of the DCM_TAP at the specific voltage and temperature.
The variable and direct phase-shift modes are controlled by the PSEN, PSINCDEC,
PSCLK, and PSDONE ports. In addition, a phase-shift overflow (DO[0]) status indicates
when the phase-shift counter has reached the end of the phase-shift delay line or the
maximum value (±255 for variable mode, +1023 for direct mode).
After the DCM locks, the initial phase in the VARIABLE_POSITIVE and
VARIABLE_CENTER modes is determined by the PHASE_SHIFT value. The initial phase
in the DIRECT mode is always 0, regardless of the value specified by the PHASE_SHIFT
attribute. The phase of the DCM output clock is incremented/decremented according to
the interaction of PSEN, PSINCDEC, PSCLK, and PSDONE from the initial or dynamically
reconfigured phase.
PSEN, PSINCDEC, and PSDONE are synchronous to PSCLK. When PSEN is asserted for
one PSCLK clock period, a phase-shift increment/decrement is initiated. When
PSINCDEC is High, an increment is initiated and when PSINCDEC is Low, a decrement is
initiated. Each increment adds to the phase shift of DCM clock outputs by 1/256 of the
CLKIN period. Similarly, each decrement decreases the phase shift by 1/256 of the CLKIN
period. PSEN must be active for exactly one PSCLK period; otherwise, a single phase-shift
increment/decrement is not guaranteed. PSDONE is High for exactly one clock period
when the phase shift is complete. The time required to complete a phase-shift operation
varies. As a result, PSDONE must be monitored for phase-shift status. Between enabling
PSEN and PSDONE is flagged, the DCM output clocks gradually change from their
original phase shift to the incremented/decremented phase shift. The completion of the
increment or decrement is signaled when PSDONE asserts High. After PSDONE has
pulsed High, another increment/decrement can be initiated.
Figure 2-6
When PSEN is activated after the phase-shift counter has reached the maximum value of
PHASE_SHIFT, the PSDONE is still pulsed High for one PSCLK period some time after the
PSEN is activated (as illustrated in
STATUS(0), or DO(0) is High to flag this condition, and no phase adjustment is performed.
illustrates the interaction of phase-shift ports.
Figure 2-6: Phase-Shift Timing Diagram
www.xilinx.com
Figure
CC
/temperature results in a phase-shift change
2-6). However, the phase-shift overflow pin,
DCM Design Guidelines
ug190_2_06_032506
71