XC5VLX50T-2FFG665I Xilinx Inc, XC5VLX50T-2FFG665I Datasheet - Page 21

IC FPGA VIRTEX-5 50K 665FCBGA

XC5VLX50T-2FFG665I

Manufacturer Part Number
XC5VLX50T-2FFG665I
Description
IC FPGA VIRTEX-5 50K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr

Specifications of XC5VLX50T-2FFG665I

Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
2211840
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
665-BBGA, FCBGA
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
X-Ref Target - Figure 7
+V
0
P–N
–V
Figure 7: Peak-to-Peak Differential Output Voltage
Table 41
summarizes the DC specifications of the clock input of the GTX_DUAL tile.
voltage swing.
Figure 9
shows the peak-to-peak differential clock input voltage swing. Consult UG198: Virtex-5 FPGA
RocketIO GTX Transceiver User Guide for further details.
Table 41: GTX_DUAL Tile Clock DC Input Level Specification
Symbol
DC Parameter
V
Differential peak-to-peak input voltage
IDIFF
V
Single-ended input voltage
ISE
R
Differential input resistance
IN
C
Required external AC coupling capacitor
EXT
Notes:
1.
V
= 0V and V
= 1200mV
MIN
MAX
X-Ref Target - Figure 8
+V
P
N
0
Figure 8: Single-Ended Clock Input Voltage Swing Peak-to-Peak
X-Ref Target - Figure 9
+V
P – N
0
–V
Figure 9: Differential Clock Input Voltage Swing Peak-to-Peak
DS202 (v5.3) May 5, 2010
Product Specification
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Figure 8
(1)
Conditions
Min
210
105
90
www.xilinx.com
DV
PPOUT
ds202_02_081809
shows the single-ended input
Typ
Max
Units
800
2000
mV
400
1000
mV
Ω
105
130
100
nF
V
ISE
ds202_03_052708
V
IDIFF
ds202_04_052708
21

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