XC5VSX50T-2FF665C Xilinx Inc, XC5VSX50T-2FF665C Datasheet - Page 7

• Manufacturer Part Number: XC5VSX50T-2FF665C
• Description: IC FPGA VIRTEX-5 50K 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 SXTr

Specifications of XC5VSX50T-2FF665C

• Number Of Logic Elements/cells: 52224
• Number Of Labs/clbs: 4080
• Total Ram Bits: 4866048
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• For Use With: HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Virtex-5 FPGA Features
This section briefly describes the features of the Virtex-5 family of FPGAs.
Input/Output Blocks (SelectIO)
IOBs are programmable and can be categorized as follows:
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The IOB registers are either edge-triggered D-type flip-flops
or level-sensitive latches.
IOBs support the following single-ended standards:
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The Digitally Controlled Impedance (DCI) I/O feature can be
configured to provide on-chip termination for each
single-ended I/O standard and some differential I/O
standards.
The IOB elements also support the following differential
signaling I/O standards:
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Two adjacent pads are used for each differential pair. Two or
four IOB blocks connect to one switch matrix to access the
routing resources.
Per-bit deskew circuitry allows for programmable signal
delay internal to the FPGA. Per-bit deskew flexibly provides
fine-grained increments of delay to carefully produce a
range of signal delays. This is especially useful for
synchronizing signal edges in source-synchronous
interfaces.
General purpose I/O in select locations (eight per bank) are
designed to be “regional clock capable” I/O by adding
special hardware connections for I/O in the same locality.
These regional clock inputs are distributed within a limited
region to minimize clock skew between IOBs. Regional I/O
clocking supplements the global clocking resources.
DS100 (v5.0) February 6, 2009
Product Specification
Programmable single-ended or differential (LVDS)
operation
Input block with an optional single data rate (SDR) or
double data rate (DDR) register
Output block with an optional SDR or DDR register
Bidirectional block
Per-bit deskew circuitry
Dedicated I/O and regional clocking resources
Built-in data serializer/deserializer
LVTTL
LVCMOS (3.3V, 2.5V, 1.8V, 1.5V, and 1.2V)
PCI (33 and 66 MHz)
PCI-X
GTL and GTLP
HSTL 1.5V and 1.8V (Class I, II, III, and IV)
HSTL 1.2V (Class 1)
SSTL 1.8V and 2.5V (Class I and II)
LVDS and Extended LVDS (2.5V only)
BLVDS (Bus LVDS)
ULVDS
Hypertransport™
Differential HSTL 1.5V and 1.8V (Class I and II)
Differential SSTL 1.8V and 2.5V (Class I and II)
RSDS (2.5V point-to-point)
R
www.xilinx.com
Data serializer/deserializer capability is added to every I/O
to support source-synchronous interfaces. A serial-to-
parallel converter with associated clock divider is included
in the input path, and a parallel-to-serial converter in the
output path.
An in-depth guide to the Virtex-5 FPGA IOB is found in the
Virtex-5 FPGA Tri-Mode Ethernet MAC User Guide.
Configurable Logic Blocks (CLBs)
A Virtex-5 FPGA CLB resource is made up of two slices.
Each slice is equivalent and contains:
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The function generators are configurable as 6-input LUTs or
dual-output 5-input LUTs. SLICEMs in some CLBs can be
configured to operate as 32-bit shift registers (or 16-bit x 2
shift registers) or as 64-bit distributed RAM. In addition, the
four storage elements can be configured as either
edge-triggered D-type flip-flops or level sensitive latches.
Each CLB has internal fast interconnect and connects to a
switch matrix to access general routing resources.
The Virtex-5 FPGA CLBs are further discussed in the
Virtex-5 FPGA User Guide.
Block RAM
The 36 Kbit true dual-port RAM block resources are
programmable from 32K x 1 to 512 x 72, in various depth
and width configurations. In addition, each 36-Kbit block
can also be configured to operate as two, independent 18-
Kbit dual-port RAM blocks.
Each port is totally synchronous and independent, offering
three “read-during-write” modes. Block RAM is cascadable
to implement large embedded storage blocks. Additionally,
back-end pipeline registers, clock control circuitry, built-in
FIFO support, ECC, and byte write enable features are also
provided as options.
The block RAM feature in Virtex-5 devices is further
discussed in the Virtex-5 FPGA User Guide.
Four function generators
Four storage elements
Arithmetic logic gates
Large multiplexers
Fast carry look-ahead chain
Virtex-5 Family Overview
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