IC FPGA VIRTEX-5 50K 665FCBGA

XC5VSX50T-2FF665C

Manufacturer Part NumberXC5VSX50T-2FF665C
DescriptionIC FPGA VIRTEX-5 50K 665FCBGA
ManufacturerXilinx Inc
SeriesVirtex™-5 SXT
XC5VSX50T-2FF665C datasheets
Product Change Notification
 


Specifications of XC5VSX50T-2FF665C

Number Of Logic Elements/cells52224Number Of Labs/clbs4080
Total Ram Bits4866048Number Of I /o360
Voltage - Supply0.95 V ~ 1.05 VMounting TypeSurface Mount
Operating Temperature0°C ~ 85°CPackage / Case665-BBGA, FCBGA
For Use WithHW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5Lead Free Status / RoHS StatusContains lead / RoHS non-compliant
Number Of Gates-  
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X-Ref Target - Figure 2
+V
0
P–N
–V
Figure 2: Peak-to-Peak Differential Output Voltage
Table 29
summarizes the DC specifications of the clock input of the GTP_DUAL tile.
voltage swing.
Figure 4
shows the peak-to-peak differential clock input voltage swing. Consult UG196: Virtex-5 FPGA
RocketIO GTP Transceiver User Guide for further details.
Table 29: GTP_DUAL Tile Clock DC Input Specifications
Symbol
DC Parameter
V
Differential peak-to-peak input voltage
IDIFF
V
Single-ended input voltage
ISE
R
Differential input resistance
IN
C
Required external AC coupling capacitor
EXT
Notes:
1.
V
= 0V and V
= 1200mV
MIN
MAX
X-Ref Target - Figure 3
+V
P
N
0
Figure 3: Single-Ended Clock Input Voltage Swing Peak-to-Peak
X-Ref Target - Figure 4
+V
P – N
0
–V
Figure 4: Differential Clock Input Voltage Swing Peak-to-Peak
DS202 (v5.3) May 5, 2010
Product Specification
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Figure 3
(1)
Conditions
Min
200
100
80
75
www.xilinx.com
DV
PPOUT
ds202_02_081809
shows the single-ended input
Typ
Max
Units
800
2000
mV
400
1000
mV
Ω
105
130
100
200
nF
V
ISE
ds202_03_052708
V
IDIFF
ds202_04_052708
15