XC5VSX50T-2FF665C Xilinx Inc, XC5VSX50T-2FF665C Datasheet - Page 16

IC FPGA VIRTEX-5 50K 665FCBGA

XC5VSX50T-2FF665C

Manufacturer Part Number
XC5VSX50T-2FF665C
Description
IC FPGA VIRTEX-5 50K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr

Specifications of XC5VSX50T-2FF665C

Number Of Logic Elements/cells
52224
Number Of Labs/clbs
4080
Total Ram Bits
4866048
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
For Use With
HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
XC5VSX50T-2FF665C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VSX50T-2FF665C
Manufacturer:
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GTP_DUAL Tile Switching Characteristics
Consult UG196:Virtex-5 FPGA RocketIO GTP Transceiver User Guide for further information.
Table 30: GTP_DUAL Tile Performance
Table 31: Dynamic Reconfiguration Port (DRP) in the GTP_DUAL Tile Switching Characteristics
Table 32: GTP_DUAL Tile Reference Clock Switching Characteristics
X-Ref Target - Figure 5
DS202 (v5.3) May 5, 2010
Product Specification
Notes:
1.
2.
3.
F
F
F
F
Symbol
GTPMAX
GPLLMAX
GPLLMIN
GTPDRPCLK
T
T
F
T
T
T
T
DCREF
PHASE
Symbol
GCLK
LOCK
Symbol
RCLK
FCLK
GJTT
The clock from the GTP_DUAL differential clock pin pair can be used for all serial bit rates. GREFCLK can be used for serial bit rates up to
1 Gb/s.
For reference clock rates above 325 MHz, a duty cycle of 45% to 55% must be maintained.
Measured at the package pin. GTP_DUAL jitter characteristics measured using a clock with specification T
Reference clock frequency range
Reference clock rise time
Reference clock fall time
Reference clock duty cycle
Reference clock total jitter, peak-peak
Clock recovery frequency acquisition
time
Clock recovery phase acquisition time
GTP DCLK (DRP clock) maximum frequency
Maximum GTP transceiver data rate
Maximum PLL frequency
Minimum PLL frequency
80%
20%
Description
T
FCLK
(2)
Figure 5: Reference Clock Timing Parameters
(1)
Description
Description
(3)
CLK
20% – 80%
80% – 20%
CLK
CLK
Initial PLL lock
Lock to data after PLL has
locked to the reference clock
T
www.xilinx.com
RCLK
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Conditions
Min
60
40
3.75
200
2.0
1.0
-3
-3
ds202_05_100506
All Speed Grades
Speed Grade
Speed Grade
Typ
200
200
GJTT
50
3.75
175
2.0
1.0
-2
-2
.
Max
350
400
400
200
60
40
3.2
2.0
1.0
150
1
-1
-1
Units
Units
Units
Gb/s
GHz
GHz
MHz
MHz
ms
ps
ps
ps
µs
%
16

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