XC5VSX50T-2FF665C Xilinx Inc, XC5VSX50T-2FF665C Datasheet - Page 49

IC FPGA VIRTEX-5 50K 665FCBGA

XC5VSX50T-2FF665C

Manufacturer Part Number
XC5VSX50T-2FF665C
Description
IC FPGA VIRTEX-5 50K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr

Specifications of XC5VSX50T-2FF665C

Number Of Logic Elements/cells
52224
Number Of Labs/clbs
4080
Total Ram Bits
4866048
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
For Use With
HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Table 69: DSP48E Switching Characteristics (Cont’d)
DS202 (v5.3) May 5, 2010
Product Specification
TDSPCCK_CEMM/TDSPCKC_CEMM
TDSPCCK_CEPP/TDSPCKC_CEPP
Setup and Hold Times of the RST Pins
TDSPCCK_{RSTAA, RSTBB}/
TDSPCKC_{RSTAA, RSTBB}
TDSPCCK_RSTCC/ TDSPCKC_RSTCC
TDSPCCK_RSTMM/ TDSPCKC_RSTMM
TDSPCCK_RSTPP/TDSPCKC_RSTPP
Combinatorial Delays from Input Pins to Output Pins
TDSPDO_{AP, ACRYOUT, BP, BCRYOUT}_M
TDSPDO_{AP, ACRYOUT, BP, BCRYOUT}_NM
TDSPDO_{CP, CCRYOUT, CRYINP, CRYINCRYOUT}
Combinatorial Delays from Input Pins to Cascading Output Pins
TDSPDO_{AACOUT, BBCOUT}
TDSPDO_{APCOUT, ACRYCOUT, AMULTSIGNOUT,
BPCOUT, BCRYCOUT, BMULTSIGNOUT}_M
TDSPDO_{APCOUT, ACRYCOUT, AMULTSIGNOUT,
BPCOUT, BCRYCOUT, BMULTSIGNOUT}_NM
TDSPDO_{CPCOUT, CCRYCOUT, CMULTSIGNOUT,
CRYINPCOUT, CRYINCRYCOUT,
CRYINMULTSIGNOUT}
Combinatorial Delays from Cascading Input Pins to All Output Pins
TDSPDO_{ACINP, ACINCRYOUT, BCINP,
BCINCRYOUT}_M
TDSPDO_{ACINP, ACINCRYOUT, BCINP,
BCINCRYOUT}_NM
TDSPDO_{ACINACOUT, BCINBCOUT}
TDSPDO_{ACINPCOUT, ACINCRYCOUT,
ACINMULTSIGNOUT, BCINPCOUT, BCINCRYCOUT,
BCINMULTSIGNOUT}_M
TDSPDO_{ACINPCOUT, ACINCRYCOUT,
ACINMULTSIGNOUT, BCINPCOUT, BCINCRYCOUT,
BCINMULTSIGNOUT}_NM
TDSPDO_{PCINP, CRYCINP, MULTSIGNINP,
PCINCRYOUT, CRYCINCRYOUT,
MULTSIGNINCRYOUT}
Symbol
RSTP input to P register CLK
CEM input to M register CLK
CEP input to P register CLK
{RSTA, RSTB} input to {A, B} register
CLK
RSTC input to C register CLK
RSTM input to M register CLK
{A, B} input to {P, CARRYOUT} output
using multiplier
{A, B} input to {P, CARRYOUT} output
not using multiplier
{C, CARRYIN} input to
{P, CARRYOUT} output
{A, B} input to
{ACOUT, BCOUT} output
{A, B} input to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT}
output using multiplier
{A, B} input to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT}
output not using multiplier
{C, CARRYIN} input to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT}
output
{ACIN, BCIN} input to {P, CARRYOUT}
output using multiplier
{ACIN, BCIN} input to {P, CARRYOUT}
output not using multiplier
{ACIN, BCIN} input to {ACOUT, BCOUT}
output
{ACIN, BCIN} input to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT}
output using multiplier
{ACIN, BCIN} input to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT}
output not using multiplier
{PCIN, CARRYCASCIN, MULTSIGNIN}
input to {P, CARRYOUT} output
www.xilinx.com
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Description
0.25
0.18
0.56
0.01
0.24
0.23
0.19
0.17
0.25
0.18
0.56
0.01
2.78
1.59
1.50
1.00
2.78
1.72
1.63
2.78
1.59
1.00
2.78
1.72
1.30
-3
Speed
0.29
0.21
0.63
0.01
0.28
0.26
0.21
0.21
0.29
0.21
0.63
0.01
3.22
1.77
1.67
1.12
3.22
1.92
1.82
3.22
1.77
1.12
3.22
1.92
1.45
-2
0.36
0.26
0.73
0.01
0.33
0.31
0.26
0.28
0.36
0.26
0.73
0.01
3.84
2.22
2.08
1.31
3.84
2.42
2.28
3.84
2.22
1.31
3.84
2.42
1.82
-1
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
49

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