IC FPGA VIRTEX-5 50K 665FCBGA

XC5VSX50T-2FF665C

Manufacturer Part NumberXC5VSX50T-2FF665C
DescriptionIC FPGA VIRTEX-5 50K 665FCBGA
ManufacturerXilinx Inc
SeriesVirtex™-5 SXT
XC5VSX50T-2FF665C datasheets
Product Change Notification
 


Specifications of XC5VSX50T-2FF665C

Number Of Logic Elements/cells52224Number Of Labs/clbs4080
Total Ram Bits4866048Number Of I /o360
Voltage - Supply0.95 V ~ 1.05 VMounting TypeSurface Mount
Operating Temperature0°C ~ 85°CPackage / Case665-BBGA, FCBGA
For Use WithHW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5Lead Free Status / RoHS StatusContains lead / RoHS non-compliant
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Table 70: Configuration Switching Characteristics (Cont’d)
Symbol
BPI Master Flash Mode Programming Switching
(4)
T
BPICCO
T
/T
BPIDCC
BPICCD
T
INITADDR
SPI Master Flash Mode Programming Switching
T
/T
SPIDCC
SPIDCCD
T
SPICCM
T
SPICCFC
T
/T
FSINIT
FSINITH
CCLK Output (Master Modes)
T
MCCKL
T
MCCKH
CCLK Input (Slave Modes)
T
SCCKL
T
SCCKH
Dynamic Reconfiguration Port (DRP) for DCM and PLL Before and After DCLK
F
DCK
T
/T
DMCCK_DADDR
DMCKC_DADDR
T
/T
DMCCK_DI
DMCKC_DI
T
/T
DMCCK_DEN
DMCKC_DEN
T
/T
DMCCK_DWE
DMCKC_DWE
T
DMCKO_DO
T
DMCKO_DRDY
Notes:
1.
Maximum frequency and setup/hold timing parameters are for 3.3V and 2.5V configuration voltages.
2.
To support longer delays in configuration, use the design solutions described in UG190: Virtex-5 FPGA User Guide
3.
DO will hold until next DRP operation.
4.
Only during configuration, the last edge is determined by a weak pull-up/pull-down resistor in the I/O.
DS202 (v5.3) May 5, 2010
Product Specification
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Description
ADDR[25:0], RS[1:0], FCS_B, FOE_B,
FWE_B outputs valid after CCLK rising edge
Setup/Hold on D[15:0] data input pins
Minimum period of initial ADDR[25:0] address
cycles
DIN Setup/Hold before/after the rising CCLK
edge
MOSI clock to out
FCS_B clock to out
FS[2:0] to INIT_B rising edge Setup and Hold
Master CCLK clock minimum Low time
Master CCLK clock minimum High time
Slave CCLK clock minimum Low time
Slave CCLK clock minimum High time
Maximum frequency for DCLK
DADDR Setup/Hold
DI Setup/Hold
DEN Setup/Hold time
DWE Setup/Hold time
(3)
CLK to out of DO
CLK to out of DRDY
www.xilinx.com
Speed Grade
Units
-3
-2
-1
10
10
10
ns
3.0
3.0
3.0
ns
0.5
0.5
0.5
3.0
3.0
3.0
CCLK cycles
4.0
4.0
4.0
ns
0.0
0.0
0.0
10
10
10
ns
10
10
10
ns
2
2
2
µs
3.0
3.0
3.0
ns, Min
3.0
3.0
3.0
ns, Min
2.0
2.0
2.0
ns, Min
2.0
2.0
2.0
ns, Min
500
450
400
MHz
1.2
1.35
1.56
ns
0.0
0.0
0.0
1.2
1.35
1.56
ns
0.0
0.0
0.0
1.2
1.35
1.56
ns
0.0
0.0
0.0
1.2
1.35
1.56
ns
0.0
0.0
0.0
1.0
1.12
1.3
ns
1.0
1.12
1.3
ns
.
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