XC5VSX50T-1FF665I Xilinx Inc, XC5VSX50T-1FF665I Datasheet - Page 21

IC FPGA VIRTEX-5 50K 665FCBGA

XC5VSX50T-1FF665I

Manufacturer Part Number
XC5VSX50T-1FF665I
Description
IC FPGA VIRTEX-5 50K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr

Specifications of XC5VSX50T-1FF665I

Number Of Logic Elements/cells
52224
Number Of Labs/clbs
4080
Total Ram Bits
4866048
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
665-BBGA, FCBGA
For Use With
HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-

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X-Ref Target - Figure 7
Table 41
voltage swing.
RocketIO GTX Transceiver User Guide for further details.
Table 41: GTX_DUAL Tile Clock DC Input Level Specification
X-Ref Target - Figure 8
X-Ref Target - Figure 9
DS202 (v5.3) May 5, 2010
Product Specification
Notes:
1.
Symbol
V
V
+V
–V
MIN
+V
+V
C
–V
V
R
IDIFF
0
EXT
0
0
ISE
IN
summarizes the DC specifications of the clock input of the GTX_DUAL tile.
= 0V and V
Figure 9
P
N
P–N
Differential peak-to-peak input voltage
Single-ended input voltage
Differential input resistance
Required external AC coupling capacitor
MAX
= 1200mV
shows the peak-to-peak differential clock input voltage swing. Consult UG198: Virtex-5 FPGA
Figure 8: Single-Ended Clock Input Voltage Swing Peak-to-Peak
Figure 9: Differential Clock Input Voltage Swing Peak-to-Peak
P – N
DC Parameter
Figure 7: Peak-to-Peak Differential Output Voltage
www.xilinx.com
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
(1)
Conditions
Figure 8
Min
210
105
90
shows the single-ended input
Typ
800
400
105
100
2000
1000
Max
130
ds202_02_081809
ds202_03_052708
ds202_04_052708
DV
V
V
PPOUT
IDIFF
ISE
Units
mV
mV
nF
Ω
21

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