XC2VP50-7FFG1152C | |
|---|---|
| Manufacturer Part Number | XC2VP50-7FFG1152C |
| Description | IC FPGA VIRTEX-II PRO 1152-FBGA |
| Manufacturer | Xilinx Inc |
| Series | Virtex™-II Pro |
| XC2VP50-7FFG1152C datasheets |
|
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Specifications of XC2VP50-7FFG1152C | |||
|---|---|---|---|
| Number Of Logic Elements/cells | 53136 | Number Of Labs/clbs | 5904 |
| Total Ram Bits | 4276224 | Number Of I /o | 692 |
| Voltage - Supply | 1.425 V ~ 1.575 V | Mounting Type | Surface Mount |
| Operating Temperature | 0°C ~ 85°C | Package / Case | 1152-BBGA, FCBGA |
| Lead Free Status / RoHS Status | Lead free / RoHS Compliant | Number Of Gates | - |
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PrevNext
R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
I/O Standard Adjustment Measurement Methodology
Input Delay Measurements
Table 36
shows the test setup parameters used for measuring Input standard adjustments (see
Table 36: Input Delay Measurement Methodology
Description
LVTTL (Low-Voltage Transistor-Transistor Logic)
LVCMOS (Low-Voltage CMOS), 3.3V
LVCMOS, 2.5V
LVCMOS, 1.8V
LVCMOS, 1.5V
PCI (Peripheral Component Interface), 33 MHz, 3.3V
PCI, 66 MHz, 3.3V
PCI-X, 133 MHz, 3.3V
GTL (Gunning Transceiver Logic)
GTL Plus
HSTL (High-Speed Transceiver Logic), Class I & II
HSTL, Class III & IV
HSTL, Class I & II, 1.8V
HSTL, Class III & IV, 1.8V
SSTL (Stub Terminated Tnscvr Logic), Class I & II, 2.5V
SSTL, Class I & II, 1.8V
LVDS (Low-Voltage Differential Signaling), 2.5V
LVDSEXT (LVDS Extended Mode), 2.5V
ULVDS (Ultra LVDS), 2.5V
LDT (HyperTransport), 2.5V
LVPECL (Low-Voltage Positive Electron-Coupled Logic), 2.5V
Notes:
1.
Input delay measurement methodology parameters for LVDCI and HSLVDCI are the same as for LVCMOS standards of the same voltage.
Parameters for all other DCI standards are the same as for the corresponding non-DCI standards.
2.
Input waveform switches between V
and V
L
3.
Measurements are made at typical, minimum, and maximum V
listed are typical. See
Virtex-II Pro Platform FPGA User Guide
4.
Input voltage level from which measurement starts.
5.
Note that this is an input voltage reference that bears no relation to the V
DS083 (v4.7) November 5, 2007
Product Specification
IOSTANDARD
Attribute
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
PCI33_3
PCI66_3
PCIX
GTL
GTLP
HSTL_I, HSTL_II
HSTL_III, HSTL_IV
HSTL_I_18, HSTL_II_18
HSTL_III_18, HSTL_IV_18
SSTL2_I, SSTL2_II
SSTL18_I, SSTL18_II
LVDS_25
LVDSEXT_25
ULVDS_25
LDT_25
LVPECL_25
.
H
values. Reported delays reflect worst case of these measurements. V
REF
for min/max specifications.
/ V
parameters found in IBIS models and/or noted in
REF
MEAS
www.xilinx.com
Table 33, page
23).
V
MEAS
(1,2)
(1,2)
V
V
(1,4,5)
(1,3,5)
L
H
0
3.3
1.65
0
3.3
1.65
0
2.5
1.25
0
1.8
0.9
0
1.5
0.75
Per PCI Specification
Per PCI Specification
Per PCI-X Specification
V
– 0.2
V
+ 0.2
V
REF
REF
REF
V
– 0.2
V
+ 0.2
V
REF
REF
REF
V
– 0.5
V
+ 0.5
V
REF
REF
REF
V
– 0.5
V
+ 0.5
V
REF
REF
REF
V
– 0.5
V
+ 0.5
V
REF
REF
REF
V
– 0.5
V
+ 0.5
V
REF
REF
REF
V
– 0.75
V
+ 0.75
V
REF
REF
REF
V
– 0.5
V
+ 0.5
V
REF
REF
REF
1.2 – 0.125
1.2 + 0.125
1.2
1.2 – 0.125
1.2 + 0.125
1.2
0.6 – 0.125
0.6 + 0.125
0.6
0.6 – 0.125
0.6 + 0.125
0.6
1.15 – 0.3
1.15 + 0.3
1.15
REF
Figure
Module 3 of 4
V
REF
–
–
–
–
–
–
–
–
0.80
1.0
0.75
0.90
0.90
1.08
1.25
0.9
values
6.
29
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